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Commit 01231088 authored by BRONES Romain's avatar BRONES Romain
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Major clean 

* Update documentation
* Top level uses bpmframe stream package
* Remove unused files (quad common will be moved in application)
* Capitalization killer for RDL file ;)
* Change package version name, decomment the C_ID and C_Version for the
  AXI-MM registers.
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doc/main.adoc
+ 23
− 8
View file @ 01231088
= COMBPM module documentation
// ================================================================================
== Description
This module provides several logic blocks to allow communication with BPM (Beam Position Monitor) electronics.
This has been built for a very precise situation (libera electron, damc-fmc2zup), but the architecture should allow modification and portability.
......@@ -7,6 +8,7 @@ This has been built for a very precise situation (libera electron, damc-fmc2zup)
For now, it only provides RX communication from the DLS CC protocol (ITech libera electron).
The module has been designed for DAMC-FMC2ZUP targets, populated with a 4SFP+ FMC board (CAENels).
// ================================================================================
== Overview
=== Main operation: Top level
......@@ -37,8 +39,16 @@ The module provide additionnal blocs usefull for the application.
* Frame filter
// ================================================================================
== Details
=== Protocol decoder (electron)
* CRC check. If fails: drop the frame, pulse frame_error output and increase the error counter.
* Counts and gives the number of frame in the last DLS CC sequence receive.
* DLS CC Sequence number check. If discontinuous: pulse seq_discontinuity output and increase
=== BPM frame AXIS stream
The AXIS data provided by the protocol decoder is descibed in the file _pkg_bpmframe_stream.vhd_.
......@@ -49,18 +59,23 @@ See this file to have up to date fields info.
The application needs to either implement FIFO or accepts every frame (AXIS packet).
The frame rate depends on the signal input.
=== Transceivers
=== Protocol decoder (electron)
The TCL script combpm_gtwizard.tcl is used to create the GTWizard IP, wich is instanciated in the top level.
* CRC check. If fails: drop the frame, pulse frame_error output and increase the error counter.
* Counts and gives the number of frame in the last DLS CC sequence receive.
* DLS CC Sequence number check. If discontinuous: pulse seq_discontinuity output and increase
=== AXI-MM register interface
We use DESYRDL to generate a AXI4L slave decoder.
== Future of this module
=== Frame filter
At SOLEIL, the BPM electronics will change by 2025.
At that point, it will be necessary to change the *Transceivers* and *Protocol decoder* blocs to match the new equipments.
*To be completed...*
// ================================================================================
== TODO/Future of this module
* Add configuration feature to allow the choice of the transceiver (for now only X0Y4 GTH).
* The application should be able to instanciate several transceiver interface, with one decoder for each.
* At SOLEIL, the BPM electronics will change by 2025.
At that point, it will be necessary to change the *Transceivers* and *Protocol decoder* blocs to match the new equipments.
Indicate if the number of frame in the sequence is different from last sequence.
hdl/top_combpm_electron.vhd
+ 15
− 56
View file @ 01231088
......@@ -11,8 +11,10 @@ use xpm.vcomponents.all;
library desyrdl;
use desyrdl.common.all;
use desyrdl.pkg_COMBPM.all;
use desyrdl.pkg_combpm.all;
use work.pkg_combpm_stream.all;
use work.pkg_combpm_version.all;
entity top_combpm_electron is
port(
......@@ -45,15 +47,8 @@ entity top_combpm_electron is
sfp_tx_fault : in std_logic;
-- AXIS interface
m_axis_tid : out std_logic_vector(0 downto 0);
m_axis_tdest : out std_logic_vector(9 downto 0);
m_axis_tdata : out std_logic_vector(127 downto 0);
m_axis_tstrb : out std_logic_vector(15 downto 0);
m_axis_tkeep : out std_logic_vector(15 downto 0);
m_axis_tlast : out std_logic;
m_axis_tuser : out std_logic_vector(0 downto 0);
m_axis_tvalid : out std_logic;
m_axis_tready : in std_logic;
m_axis_m2s : out t_bpmframe_axis_m2s;
m_axis_s2m : in t_bpmframe_axis_s2m; -- warning: TREADY is ignored !
-- AXI bus interface
pi_s_top : in t_COMBPM_m2s;
......@@ -63,30 +58,6 @@ end top_combpm_electron;
architecture struct of top_combpm_electron is
--------------------------
-- INTERFACE ATTRIBUTES --
--------------------------
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO of rst_n : SIGNAL is "xilinx.com:signal:reset:1.0 rst_n RST";
ATTRIBUTE X_INTERFACE_PARAMETER of rst_n : SIGNAL is "POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO of qpll_reset : SIGNAL is "xilinx.com:signal:reset:1.0 qpll_reset RST";
ATTRIBUTE X_INTERFACE_PARAMETER of qpll_reset : SIGNAL is "POLARITY ACTIVE_HIGH";
ATTRIBUTE X_INTERFACE_PARAMETER of free_100_clk: SIGNAL is "FREQ_HZ 100000000";
ATTRIBUTE X_INTERFACE_PARAMETER of clk: SIGNAL is "FREQ_HZ 156250000, ASSOCIATED_BUSIF m_axis:s_axi";
ATTRIBUTE X_INTERFACE_INFO of sfp_txn: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TXN";
ATTRIBUTE X_INTERFACE_INFO of sfp_rxn: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp RXN";
ATTRIBUTE X_INTERFACE_INFO of sfp_txp: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TXP";
ATTRIBUTE X_INTERFACE_INFO of sfp_rxp: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp RXP";
ATTRIBUTE X_INTERFACE_INFO of sfp_rx_los: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp RX_LOS";
ATTRIBUTE X_INTERFACE_INFO of sfp_mod_abs: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp MOD_ABS";
ATTRIBUTE X_INTERFACE_INFO of sfp_tx_disable: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TX_DISABLE";
ATTRIBUTE X_INTERFACE_INFO of sfp_tx_fault: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TX_FAULT";
COMPONENT combpm_gtwizard
PORT (
gtwiz_userclk_tx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
......@@ -148,8 +119,8 @@ architecture struct of top_combpm_electron is
------------------------
-- SIGNAL DECLARATION --
------------------------
signal sync_resetn : std_logic;
signal sync_reset : std_logic;
signal sync_resetn : std_logic; -- This is async reset with sync deassertion
signal sync_reset : std_logic; -- This is async reset with sync deassertion
signal usrclk : std_logic;
signal rst : std_logic;
......@@ -170,14 +141,13 @@ architecture struct of top_combpm_electron is
signal gt_rxbyterealign : std_logic;
signal gt_rxcommadet : std_logic;
signal interface_ready : std_logic;
signal addrmap_w : t_addrmap_COMBPM_in;
signal addrmap_r : t_addrmap_COMBPM_out;
signal addrmap_w : t_addrmap_combpm_in;
signal addrmap_r : t_addrmap_combpm_out;
begin
-- This CDC is used to deassert async reset in sync with the transceiver clock.
xpm_cdc_async_rst_inst : xpm_cdc_async_rst
generic map (
DEST_SYNC_FF => 4,
......@@ -212,9 +182,6 @@ begin
-- SFP direct connexion
sfp_tx_disable <= '1';
-- Interface Ready signal combinatorial
interface_ready <= gt_powergood and gt_rxresetdone and gt_rxbyteisaligned and qpll_lock;
----------------------
-- AXI-MM INTERFACE --
----------------------
......@@ -231,8 +198,8 @@ begin
);
--addrmap_w.ID.data.data <= C_ID;
--addrmap_w.VERSION.data.data <= C_VERSION;
addrmap_w.ID.data.data <= C_ID;
addrmap_w.VERSION.data.data <= C_VERSION;
addrmap_w.SFP.RXLOS.data(0) <= sfp_rx_los;
addrmap_w.SFP.MODABS.data(0) <= sfp_mod_abs;
addrmap_w.GT.POWERGOOD.data(0) <= gt_powergood;
......@@ -254,17 +221,9 @@ begin
clk => usrclk,
pps => pps,
gt_datarx => gt_datarx,
gt_interfaceready => interface_ready,
m_axi_tid => m_axis_tid,
m_axi_tdest => m_axis_tdest,
m_axi_tdata => m_axis_tdata,
m_axi_tstrb => m_axis_tstrb,
m_axi_tkeep => m_axis_tkeep,
m_axi_tlast => m_axis_tlast,
m_axi_tuser => m_axis_tuser,
m_axi_tvalid => m_axis_tvalid,
m_axi_tready => m_axis_tready,
m_axis_m2s => m_axis_m2s,
m_axis_s2m => m_axis_s2m,
mc_time => mc_time,
soft_reset => addrmap_w.PROTOCOL.SOFTRESET.data(0),
......
others/combpm_gtwizard_gthe4_common_wrapper.v deleted 100644 → 0
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others/gthe_common.vhd deleted 100644 → 0
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library ieee;
use ieee.std_logic_1164.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity gthe_common is
port(
-- Differential clock intput
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
-- Detection features
freerun_clk : in std_logic;
-- Buffered ref
buff_gtrefclk : out std_logic;
-- QPLL0 interface
qpll0reset : in std_logic;
qpll0lock : out std_logic;
qpll0outclk : out std_logic;
qpll0refclk : out std_logic;
qpll0fblost : out std_logic;
qpll0reflost : out std_logic;
-- QPLL0 interface
qpll1reset : in std_logic;
qpll1lock : out std_logic;
qpll1outclk : out std_logic;
qpll1refclk : out std_logic;
qpll1fblost : out std_logic;
qpll1reflost : out std_logic
);
end entity gthe_common;
architecture struct of gthe_common is
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of gtrefclk_p: SIGNAL is "xilinx.com:interface:diff_clock:1.0 gtrefclk_diff CLK_P";
ATTRIBUTE X_INTERFACE_INFO of gtrefclk_n: SIGNAL is "xilinx.com:interface:diff_clock:1.0 gtrefclk_diff CLK_N";
signal gtrefclk : std_logic;
signal gtrefclk_out2 : std_logic;
component combpm_gtwizard_gthe4_common_wrapper
port(
GTHE4_COMMON_BGBYPASSB : in std_logic_vector(0 downto 0);
GTHE4_COMMON_BGMONITORENB : in std_logic_vector(0 downto 0);
GTHE4_COMMON_BGPDB : in std_logic_vector(0 downto 0);
GTHE4_COMMON_BGRCALOVRD : in std_logic_vector(4 downto 0);
GTHE4_COMMON_BGRCALOVRDENB : in std_logic_vector(0 downto 0);
GTHE4_COMMON_DRPADDR : in std_logic_vector(15 downto 0);
GTHE4_COMMON_DRPCLK : in std_logic_vector(0 downto 0);
GTHE4_COMMON_DRPDI : in std_logic_vector(15 downto 0);
GTHE4_COMMON_DRPEN : in std_logic_vector(0 downto 0);
GTHE4_COMMON_DRPWE : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTGREFCLK0 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTGREFCLK1 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTNORTHREFCLK00 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTNORTHREFCLK01 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTNORTHREFCLK10 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTNORTHREFCLK11 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTREFCLK00 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTREFCLK01 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTREFCLK10 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTREFCLK11 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTSOUTHREFCLK00 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTSOUTHREFCLK01 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTSOUTHREFCLK10 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_GTSOUTHREFCLK11 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_PCIERATEQPLL0 : in std_logic_vector(2 downto 0);
GTHE4_COMMON_PCIERATEQPLL1 : in std_logic_vector(2 downto 0);
GTHE4_COMMON_PMARSVD0 : in std_logic_vector(7 downto 0);
GTHE4_COMMON_PMARSVD1 : in std_logic_vector(7 downto 0);
GTHE4_COMMON_QPLL0CLKRSVD0 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL0CLKRSVD1 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL0FBDIV : in std_logic_vector(7 downto 0);
GTHE4_COMMON_QPLL0LOCKDETCLK : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL0LOCKEN : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL0PD : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL0REFCLKSEL : in std_logic_vector(2 downto 0);
GTHE4_COMMON_QPLL0RESET : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1CLKRSVD0 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1CLKRSVD1 : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1FBDIV : in std_logic_vector(7 downto 0);
GTHE4_COMMON_QPLL1LOCKDETCLK : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1LOCKEN : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1PD : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1REFCLKSEL : in std_logic_vector(2 downto 0);
GTHE4_COMMON_QPLL1RESET : in std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLLRSVD1 : in std_logic_vector(7 downto 0);
GTHE4_COMMON_QPLLRSVD2 : in std_logic_vector(4 downto 0);
GTHE4_COMMON_QPLLRSVD3 : in std_logic_vector(4 downto 0);
GTHE4_COMMON_QPLLRSVD4 : in std_logic_vector(7 downto 0);
GTHE4_COMMON_RCALENB : in std_logic_vector(0 downto 0);
GTHE4_COMMON_SDM0DATA : in std_logic_vector(24 downto 0);
GTHE4_COMMON_SDM0RESET : in std_logic_vector(0 downto 0);
GTHE4_COMMON_SDM0TOGGLE : in std_logic_vector(0 downto 0);
GTHE4_COMMON_SDM0WIDTH : in std_logic_vector(1 downto 0);
GTHE4_COMMON_SDM1DATA : in std_logic_vector(24 downto 0);
GTHE4_COMMON_SDM1RESET : in std_logic_vector(0 downto 0);
GTHE4_COMMON_SDM1TOGGLE : in std_logic_vector(0 downto 0);
GTHE4_COMMON_SDM1WIDTH : in std_logic_vector(1 downto 0);
GTHE4_COMMON_TCONGPI : in std_logic_vector(9 downto 0);
GTHE4_COMMON_TCONPOWERUP : in std_logic_vector(0 downto 0);
GTHE4_COMMON_TCONRESET : in std_logic_vector(1 downto 0);
GTHE4_COMMON_TCONRSVDIN1 : in std_logic_vector(1 downto 0);
GTHE4_COMMON_DRPDO : out std_logic_vector(15 downto 0);
GTHE4_COMMON_DRPRDY : out std_logic_vector(0 downto 0);
GTHE4_COMMON_PMARSVDOUT0 : out std_logic_vector(7 downto 0);
GTHE4_COMMON_PMARSVDOUT1 : out std_logic_vector(7 downto 0);
GTHE4_COMMON_QPLL0FBCLKLOST : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL0LOCK : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL0OUTCLK : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL0OUTREFCLK : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL0REFCLKLOST : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1FBCLKLOST : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1LOCK : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1OUTCLK : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1OUTREFCLK : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLL1REFCLKLOST : out std_logic_vector(0 downto 0);
GTHE4_COMMON_QPLLDMONITOR0 : out std_logic_vector(7 downto 0);
GTHE4_COMMON_QPLLDMONITOR1 : out std_logic_vector(7 downto 0);
GTHE4_COMMON_REFCLKOUTMONITOR0 : out std_logic_vector(0 downto 0);
GTHE4_COMMON_REFCLKOUTMONITOR1 : out std_logic_vector(0 downto 0);
GTHE4_COMMON_RXRECCLK0SEL : out std_logic_vector(1 downto 0);
GTHE4_COMMON_RXRECCLK1SEL : out std_logic_vector(1 downto 0);
GTHE4_COMMON_SDM0FINALOUT : out std_logic_vector(3 downto 0);
GTHE4_COMMON_SDM0TESTDATA : out std_logic_vector(14 downto 0);
GTHE4_COMMON_SDM1FINALOUT : out std_logic_vector(3 downto 0);
GTHE4_COMMON_SDM1TESTDATA : out std_logic_vector(14 downto 0);
GTHE4_COMMON_TCONGPO : out std_logic_vector(9 downto 0);
GTHE4_COMMON_TCONRSVDOUT0 : out std_logic_vector(0 downto 0)
);
end component;
begin
-- INPUT BUFFER
IBUFDS_GTE4_inst : IBUFDS_GTE4
generic map (
REFCLK_EN_TX_PATH => '0',
REFCLK_HROW_CK_SEL => "00",
REFCLK_ICNTL_RX => "00"
)
port map (
O => gtrefclk,
ODIV2 => gtrefclk_out2,
CEB => '0',
I => gtrefclk_p,
IB => gtrefclk_n
);
BUFG_GT_inst : BUFG_GT
port map (
O => buff_gtrefclk,
CE => '1',
CEMASK => '1',
CLR => '0',
CLRMASK => '1',
DIV => "000",
I => gtrefclk_out2
);
-- TRANSCEIVER COMMON BLOCK
gthe4_common_wrapper_inst: combpm_gtwizard_gthe4_common_wrapper
port map(
GTHE4_COMMON_BGBYPASSB => "1",
GTHE4_COMMON_BGMONITORENB => "1",
GTHE4_COMMON_BGPDB => "1",
GTHE4_COMMON_BGRCALOVRD => "11111",
GTHE4_COMMON_BGRCALOVRDENB => "1",
GTHE4_COMMON_DRPADDR => "0000000000000000",
GTHE4_COMMON_DRPCLK => "0",
GTHE4_COMMON_DRPDI => "0000000000000000",
GTHE4_COMMON_DRPEN => "0",
GTHE4_COMMON_DRPWE => "0",
GTHE4_COMMON_GTGREFCLK0 => "0",
GTHE4_COMMON_GTGREFCLK1 => "0",
GTHE4_COMMON_GTNORTHREFCLK00 => "0",
GTHE4_COMMON_GTNORTHREFCLK01 => "0",
GTHE4_COMMON_GTNORTHREFCLK10 => "0",
GTHE4_COMMON_GTNORTHREFCLK11 => "0",
GTHE4_COMMON_GTREFCLK00(0) => gtrefclk,
GTHE4_COMMON_GTREFCLK01(0) => gtrefclk,
GTHE4_COMMON_GTREFCLK10 => "0",
GTHE4_COMMON_GTREFCLK11 => "0",
GTHE4_COMMON_GTSOUTHREFCLK00 => "0",
GTHE4_COMMON_GTSOUTHREFCLK01 => "0",
GTHE4_COMMON_GTSOUTHREFCLK10 => "0",
GTHE4_COMMON_GTSOUTHREFCLK11 => "0",
GTHE4_COMMON_PCIERATEQPLL0 => "000",
GTHE4_COMMON_PCIERATEQPLL1 => "000",
GTHE4_COMMON_PMARSVD0 => "00000000",
GTHE4_COMMON_PMARSVD1 => "00000000",
GTHE4_COMMON_QPLL0CLKRSVD0 => "0",
GTHE4_COMMON_QPLL0CLKRSVD1 => "0",
GTHE4_COMMON_QPLL0FBDIV => "00000000",
GTHE4_COMMON_QPLL0LOCKDETCLK(0) =>freerun_clk,
GTHE4_COMMON_QPLL0LOCKEN => "1",
GTHE4_COMMON_QPLL0PD => "0",
GTHE4_COMMON_QPLL0REFCLKSEL => "001",
GTHE4_COMMON_QPLL0RESET(0) => qpll0reset,
GTHE4_COMMON_QPLL1CLKRSVD0 => "0",
GTHE4_COMMON_QPLL1CLKRSVD1 => "0",
GTHE4_COMMON_QPLL1FBDIV => "00000000",
GTHE4_COMMON_QPLL1LOCKDETCLK(0) =>freerun_clk,
GTHE4_COMMON_QPLL1LOCKEN => "1",
GTHE4_COMMON_QPLL1PD => "0",
GTHE4_COMMON_QPLL1REFCLKSEL => "001",
GTHE4_COMMON_QPLL1RESET(0) => qpll1reset,
GTHE4_COMMON_QPLLRSVD1 => "00000000",
GTHE4_COMMON_QPLLRSVD2 => "00000",
GTHE4_COMMON_QPLLRSVD3 => "00000",
GTHE4_COMMON_QPLLRSVD4 => "00000000",
GTHE4_COMMON_RCALENB => "1",
GTHE4_COMMON_SDM0DATA => "0000000000000000000000000",
GTHE4_COMMON_SDM0RESET => "0",
GTHE4_COMMON_SDM0TOGGLE => "0",
GTHE4_COMMON_SDM0WIDTH => "00",
GTHE4_COMMON_SDM1DATA => "0010001011010000111001010",
GTHE4_COMMON_SDM1RESET => "0",
GTHE4_COMMON_SDM1TOGGLE => "0",
GTHE4_COMMON_SDM1WIDTH => "00",
GTHE4_COMMON_TCONGPI => "0000000000",
GTHE4_COMMON_TCONPOWERUP => "0",
GTHE4_COMMON_TCONRESET => "00",
GTHE4_COMMON_TCONRSVDIN1 => "00",
GTHE4_COMMON_DRPDO => open,
GTHE4_COMMON_DRPRDY => open,
GTHE4_COMMON_PMARSVDOUT0 => open,
GTHE4_COMMON_PMARSVDOUT1 => open,
GTHE4_COMMON_QPLL0FBCLKLOST(0) => qpll0fblost,
GTHE4_COMMON_QPLL0LOCK(0) => qpll0lock,
GTHE4_COMMON_QPLL0OUTCLK(0) => qpll0outclk,
GTHE4_COMMON_QPLL0OUTREFCLK(0) => qpll0refclk,
GTHE4_COMMON_QPLL0REFCLKLOST(0) => qpll0reflost,
GTHE4_COMMON_QPLL1FBCLKLOST(0) => qpll1reflost,
GTHE4_COMMON_QPLL1LOCK(0) => qpll1lock,
GTHE4_COMMON_QPLL1OUTCLK(0) => qpll1outclk,
GTHE4_COMMON_QPLL1OUTREFCLK(0) => qpll1refclk,
GTHE4_COMMON_QPLL1REFCLKLOST(0) => qpll1fblost,
GTHE4_COMMON_QPLLDMONITOR0 => open,
GTHE4_COMMON_QPLLDMONITOR1 => open,
GTHE4_COMMON_REFCLKOUTMONITOR0 => open,
GTHE4_COMMON_REFCLKOUTMONITOR1 => open,
GTHE4_COMMON_RXRECCLK0SEL => open,
GTHE4_COMMON_RXRECCLK1SEL => open,
GTHE4_COMMON_SDM0FINALOUT => open,
GTHE4_COMMON_SDM0TESTDATA => open,
GTHE4_COMMON_SDM1FINALOUT => open,
GTHE4_COMMON_SDM1TESTDATA => open,
GTHE4_COMMON_TCONGPO => open,
GTHE4_COMMON_TCONRSVDOUT0 => open
);
end architecture struct;
others/gtwizard_ultrascale_v1_7_gthe4_common.v deleted 100644 → 0
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rdl/COMBPM.rdl → rdl/combpm.rdl
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`include "COMBPM.vh" // Auto generated from FWK
`include "combpm.vh" // Auto generated from FWK
addrmap COMBPM {
addrmap combpm {
desyrdl_generate_hdl = true;
desyrdl_interface = "AXI4L";
......
scripts/add_files.tcl deleted 100644 → 0
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# This will add sources files and import IP for the com_bpm bloc
set module_root [file normalize [file dirname [file normalize [info script]]]/../]
add_files "$module_root/hdl/combpm_protocol_electron_ctrl.vhd"
add_files "$module_root/hdl/combpm_protocol_electron.vhd"
add_files "$module_root/hdl/combpm_gtwrapper.vhd"
add_files "$module_root/hdl/top_combpm_electron.vhd"
add_files "$module_root/hdl/combpm_gtwrapper_CAENELS4SFP_1L_pkg.vhd"
import_ip "$module_root/ip_cores/CAENELSSFP_1L.xci"
scripts/test.sh deleted 100755 → 0
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#!/bin/bash
# Perform compilation of all vhdl sources
# For test, only two are needed, but it helps to check syntax
# This will create xsim.dir/work
xvhdl --log test.log hdl/combpm_protocol_electron_ctrl.vhd
xvhdl --log test.log hdl/combpm_protocol_electron.vhd
xvhdl --log test.log hdl/top_combpm_electron.vhd
xvhdl --log test.log test/tb_combpm_protocol_electron.vhd
# Perform Elaboration and snapshot creation
# This will create xsim.dir/work.tb_combpm_protocol_electron
xelab tb_combpm_protocol_electron -debug typical
# Launch simulation
xsim work.tb_combpm_protocol_electron -view test/tb_combpm_protocol_electron_behav.wcfg -gui
tcl/bloc_synthesis.tcl deleted 100644 → 0
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# Source metadata
source ./tcl/metadata.tcl
# Create project
create_project synth_project -part ${part} -in_memory
set_property source_mgmt_mode All [current_project]
set_property IP_REPO_PATHS . [current_fileset]
update_ip_catalog
# Create instance of the IP
create_ip -vendor ${vlnv_vendor} -library "user" -name "combpm" -module_name combpm_0
# Generate output products
#generate_target all [get_ips combpm_0]
# Try synthesis
synth_ip [get_ips combpm_0]
close_project
tcl/combpm.tcl deleted 100644 → 0
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# Source metadata
source ./tcl/metadata.tcl
# Create project
set ip_project [create_project -name ${design} -part ${part} -in_memory ]
set_property top ${top} [current_fileset]
# Compilation order in auto
set_property source_mgmt_mode All ${ip_project}
# Read sources
source tcl/sources.tcl
# Generate Xilinx IP
source tcl/generate_gtwizard.tcl
# Compile order to auto
update_compile_order -fileset sources_1
# Package project
ipx::package_project
set ip_core [ipx::current_core]
set_property -dict ${ip_properties} ${ip_core}
set_property SUPPORTED_FAMILIES ${family_lifecycle} ${ip_core}
# Associate AX/AXIS interfaces and reset with clock
# Done in VHDL file
# Remove default address map
ipx::remove_memory_map [lindex [split [ipx::get_memory_maps]] 2] [ipx::current_core]
# Create Address map
set s_axi_mm [ipx::add_memory_map s_axi_ctrl [ipx::current_core]]
set_property slave_memory_map_ref s_axi_ctrl [ipx::get_bus_interfaces s_axi -of_objects [ipx::current_core]]
set_property ENABLEMENT_PRESENCE required ${s_axi_mm}
set s_axi_blk [ipx::add_address_block registers ${s_axi_mm}]
set_property -dict { \
ACCESS "read-write" \
DESCRIPTION "Control and status registers" \
ENABLEMENT_PRESENCE required \
NAME "registers" \
RANGE 256 \
USAGE "register" \
WIDTH 8 \
} ${s_axi_blk}
# Save IP and close project
ipx::check_integrity ${ip_core}
ipx::save_core ${ip_core}
close_project
tcl/main.tcl
+ 4
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......@@ -15,20 +15,18 @@ proc init {} {
proc setSources {} {
variable Vhdl
# Generate VHDL package with modle version
genModVerFile VHDL ../hdl/pkg_version.vhd
# Generate VHDL package with modversion
genModVerFile VHDL ../hdl/pkg_combpm_version.vhd
lappend Vhdl ../hdl/combpm_protocol_electron.vhd
lappend Vhdl ../hdl/top_combpm_electron.vhd
lappend Vhdl ../others/gthe_common.vhd
lappend Vhdl ../others/combpm_gtwizard_gthe4_common_wrapper.v
lappend Vhdl ../others/gtwizard_ultrascale_v1_7_gthe4_common.v
}
# ==============================================================================
proc setAddressSpace {} {
variable AddressSpace
addAddressSpace AddressSpace "COMBPM" RDL {} ../rdl/COMBPM.rdl
addAddressSpace AddressSpace "combpm" RDL {} ../rdl/combpm.rdl
}
# ==============================================================================
......
tcl/metadata.tcl deleted 100644 → 0
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set design "combpm"
set top top_combpm_electron
set part "xczu11eg-ffvc1760-2L-e"
set vlnv_vendor "synchrotron-soleil.fr"
set ip_properties [ list \
vendor ${vlnv_vendor} \
library "user" \
name ${design} \
version "1.0" \
taxonomy "/Communication_&_Networking/Serial_Interfaces" \
display_name "BPM Communication Decoder" \
description "Decode CC protocol (Electron) from a transceiver interface and generate AXIS frames" \
vendor_display_name "Synchrotron SOLEIL" \
company_url "http://www.synchrotron-soleil.fr" \
]
set family_lifecycle [list \
zynquplus{${part}} Beta \
]
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