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BRONES Romain authored* HTG2QSFP, on FMC1, Only 4 lanes
BRONES Romain authored* HTG2QSFP, on FMC1, Only 4 lanes
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combpm_htg2qsfp_fmc1_4L_L.vhd 26.92 KiB
library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity combpm_htg2qsfp_fmc1_4l_l is
port(
-- 100MHz clock, main ref clock
clk_100 : in std_logic;
-- User clock provided by GT
usrclk : out std_logic;
-- Async reset active low
rst_n : in std_logic;
-- Differential reference clock inputs
mgtrefclk_p : in std_logic;
mgtrefclk_n : in std_logic;
-- QSFP01 interface
qsfp01_tx1n : out std_logic;
qsfp01_tx1p : out std_logic;
qsfp01_rx1n : in std_logic;
qsfp01_rx1p : in std_logic;
qsfp01_tx2n : out std_logic;
qsfp01_tx2p : out std_logic;
qsfp01_rx2n : in std_logic;
qsfp01_rx2p : in std_logic;
qsfp01_tx3n : out std_logic;
qsfp01_tx3p : out std_logic;
qsfp01_rx3n : in std_logic;
qsfp01_rx3p : in std_logic;
qsfp01_tx4n : out std_logic;
qsfp01_tx4p : out std_logic;
qsfp01_rx4n : in std_logic;
qsfp01_rx4p : in std_logic;
qsfp01_modprsl : in std_logic;
qsfp01_resetn : out std_logic;
qsfp01_intl : in std_logic;
-- GT01 interface
gt01_datarx : out std_logic_vector(15 downto 0);
gt01_datatx : in std_logic_vector(15 downto 0);
gt01_powergood : out std_logic;
gt01_qplllock : out std_logic;
gt01_txclkactive : out std_logic;
gt01_rxclkactive : out std_logic;
gt01_txresetdone : out std_logic;
gt01_rxresetdone : out std_logic;
gt01_rxcdrlock : out std_logic;
gt01_rxbyteisaligned : out std_logic;
gt01_rxbyterealign : out std_logic;
gt01_rxcommadet : out std_logic;
gt01_txfault : out std_logic;
gt01_rxlos : out std_logic;
gt01_modabs : out std_logic;
gt01_rstall : in std_logic;
gt01_rxcommadeten : in std_logic;
gt01_txdisable : in std_logic;
-- GT02 interface
gt02_datarx : out std_logic_vector(15 downto 0);
gt02_datatx : in std_logic_vector(15 downto 0);
gt02_powergood : out std_logic;
gt02_qplllock : out std_logic;
gt02_txclkactive : out std_logic;
gt02_rxclkactive : out std_logic; gt02_txresetdone : out std_logic;
gt02_rxresetdone : out std_logic;
gt02_rxcdrlock : out std_logic;
gt02_rxbyteisaligned : out std_logic;
gt02_rxbyterealign : out std_logic;
gt02_rxcommadet : out std_logic;
gt02_txfault : out std_logic;
gt02_rxlos : out std_logic;
gt02_modabs : out std_logic;
gt02_rstall : in std_logic;
gt02_rxcommadeten : in std_logic;
gt02_txdisable : in std_logic;
-- GT03 interface
gt03_datarx : out std_logic_vector(15 downto 0);
gt03_datatx : in std_logic_vector(15 downto 0);
gt03_powergood : out std_logic;
gt03_qplllock : out std_logic;
gt03_txclkactive : out std_logic;
gt03_rxclkactive : out std_logic;
gt03_txresetdone : out std_logic;
gt03_rxresetdone : out std_logic;
gt03_rxcdrlock : out std_logic;
gt03_rxbyteisaligned : out std_logic;
gt03_rxbyterealign : out std_logic;
gt03_rxcommadet : out std_logic;
gt03_txfault : out std_logic;
gt03_rxlos : out std_logic;
gt03_modabs : out std_logic;
gt03_rstall : in std_logic;
gt03_rxcommadeten : in std_logic;
gt03_txdisable : in std_logic
);
end combpm_htg2qsfp_fmc1_4l_l;
architecture rtl of combpm_htg2qsfp_fmc1_4l_l is
--------------------------------
-- INTERFACE PORT ASSOCIATION --
--------------------------------
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
ATTRIBUTE X_INTERFACE_INFO of clk_100 : SIGNAL is "xilinx.com:signal:clock:1.0 clk_100 CLK";
ATTRIBUTE X_INTERFACE_PARAMETER of clk_100 : SIGNAL is "FREQ 100000000";
ATTRIBUTE X_INTERFACE_INFO of rst_n : SIGNAL is "xilinx.com:signal:reset:1.0 rst_n RST";
ATTRIBUTE X_INTERFACE_PARAMETER of rst_n : SIGNAL is "POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_INFO of qsfp01_tx1n : SIGNAL is "soleil:user:qsfp:1.0 QSFP01 qsfp01_tx1n";
ATTRIBUTE X_INTERFACE_INFO of qsfp01_tx1p : SIGNAL is "soleil:user:qsfp:1.0 QSFP01 qsfp01_tx1p";
ATTRIBUTE X_INTERFACE_INFO of qsfp01_rx1n : SIGNAL is "soleil:user:qsfp:1.0 QSFP01 qsfp01_rx1n";
ATTRIBUTE X_INTERFACE_INFO of qsfp01_rx1p : SIGNAL is "soleil:user:qsfp:1.0 QSFP01 qsfp01_rx1p";
ATTRIBUTE X_INTERFACE_INFO of qsfp01_tx2n : SIGNAL is "soleil:user:qsfp:1.0 QSFP01 qsfp01_tx2n";
ATTRIBUTE X_INTERFACE_INFO of qsfp01_tx2p : SIGNAL is "soleil:user:qsfp:1.0 QSFP01 qsfp01_tx2p";
ATTRIBUTE X_INTERFACE_INFO of qsfp01_rx2n : SIGNAL is "soleil:user:qsfp:1.0 QSFP01 qsfp01_rx2n";
ATTRIBUTE X_INTERFACE_INFO of qsfp01_rx2p : SIGNAL is "soleil:user:qsfp:1.0 QSFP01 qsfp01_rx2p";
ATTRIBUTE X_INTERFACE_INFO of qsfp01_tx3n : SIGNAL is "soleil:user:qsfp:1.0 QSFP01 qsfp01_tx3n";
ATTRIBUTE X_INTERFACE_INFO of qsfp01_tx3p : SIGNAL is "soleil:user:qsfp:1.0 QSFP01 qsfp01_tx3p";
ATTRIBUTE X_INTERFACE_INFO of qsfp01_rx3n : SIGNAL is "soleil:user:qsfp:1.0 QSFP01 qsfp01_rx3n";
ATTRIBUTE X_INTERFACE_INFO of qsfp01_rx3p : SIGNAL is "soleil:user:qsfp:1.0 QSFP01 qsfp01_rx3p";
ATTRIBUTE X_INTERFACE_INFO of qsfp01_tx4n : SIGNAL is "soleil:user:qsfp:1.0 QSFP01 qsfp01_tx4n";
ATTRIBUTE X_INTERFACE_INFO of qsfp01_tx4p : SIGNAL is "soleil:user:qsfp:1.0 QSFP01 qsfp01_tx4p";
ATTRIBUTE X_INTERFACE_INFO of qsfp01_rx4n : SIGNAL is "soleil:user:qsfp:1.0 QSFP01 qsfp01_rx4n";
ATTRIBUTE X_INTERFACE_INFO of qsfp01_rx4p : SIGNAL is "soleil:user:qsfp:1.0 QSFP01 qsfp01_rx4p";
ATTRIBUTE X_INTERFACE_INFO of qsfp01_modprsl : SIGNAL is "soleil:user:qsfp:1.0 QSFP01 qsfp01_modprsl";
ATTRIBUTE X_INTERFACE_INFO of qsfp01_resetn : SIGNAL is "soleil:user:qsfp:1.0 QSFP01 qsfp01_resetn";
ATTRIBUTE X_INTERFACE_INFO of qsfp01_intl : SIGNAL is "soleil:user:qsfp:1.0 QSFP01 qsfp01_intl";
ATTRIBUTE X_INTERFACE_INFO of gt01_datarx : SIGNAL is "soleil:user:gtsfp:1.0 GT01 datarx";
ATTRIBUTE X_INTERFACE_INFO of gt01_datatx : SIGNAL is "soleil:user:gtsfp:1.0 GT01 datatx";
ATTRIBUTE X_INTERFACE_INFO of gt01_powergood : SIGNAL is "soleil:user:gtsfp:1.0 GT01 powergood";
ATTRIBUTE X_INTERFACE_INFO of gt01_qplllock : SIGNAL is "soleil:user:gtsfp:1.0 GT01 qplllock";
ATTRIBUTE X_INTERFACE_INFO of gt01_txclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT01 txclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt01_txresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT01 txresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxcdrlock : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxcdrlock";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxbyteisaligned : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxbyteisaligned";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxbyterealign : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxbyterealign";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxcommadet : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxcommadet";
ATTRIBUTE X_INTERFACE_INFO of gt01_txfault : SIGNAL is "soleil:user:gtsfp:1.0 GT01 txfault";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxlos : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxlos";
ATTRIBUTE X_INTERFACE_INFO of gt01_modabs : SIGNAL is "soleil:user:gtsfp:1.0 GT01 modabs";
ATTRIBUTE X_INTERFACE_INFO of gt01_rstall : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rstall";
ATTRIBUTE X_INTERFACE_INFO of gt01_rxcommadeten : SIGNAL is "soleil:user:gtsfp:1.0 GT01 rxcommadeten";
ATTRIBUTE X_INTERFACE_INFO of gt01_txdisable : SIGNAL is "soleil:user:gtsfp:1.0 GT01 txdisable";
ATTRIBUTE X_INTERFACE_INFO of gt02_datarx : SIGNAL is "soleil:user:gtsfp:1.0 GT02 datarx";
ATTRIBUTE X_INTERFACE_INFO of gt02_datatx : SIGNAL is "soleil:user:gtsfp:1.0 GT02 datatx";
ATTRIBUTE X_INTERFACE_INFO of gt02_powergood : SIGNAL is "soleil:user:gtsfp:1.0 GT02 powergood";
ATTRIBUTE X_INTERFACE_INFO of gt02_qplllock : SIGNAL is "soleil:user:gtsfp:1.0 GT02 qplllock";
ATTRIBUTE X_INTERFACE_INFO of gt02_txclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT02 txclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt02_txresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT02 txresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxcdrlock : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxcdrlock";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxbyteisaligned : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxbyteisaligned";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxbyterealign : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxbyterealign";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxcommadet : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxcommadet";
ATTRIBUTE X_INTERFACE_INFO of gt02_txfault : SIGNAL is "soleil:user:gtsfp:1.0 GT02 txfault";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxlos : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxlos";
ATTRIBUTE X_INTERFACE_INFO of gt02_modabs : SIGNAL is "soleil:user:gtsfp:1.0 GT02 modabs";
ATTRIBUTE X_INTERFACE_INFO of gt02_rstall : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rstall";
ATTRIBUTE X_INTERFACE_INFO of gt02_rxcommadeten : SIGNAL is "soleil:user:gtsfp:1.0 GT02 rxcommadeten";
ATTRIBUTE X_INTERFACE_INFO of gt02_txdisable : SIGNAL is "soleil:user:gtsfp:1.0 GT02 txdisable";
ATTRIBUTE X_INTERFACE_INFO of gt03_datarx : SIGNAL is "soleil:user:gtsfp:1.0 GT03 datarx";
ATTRIBUTE X_INTERFACE_INFO of gt03_datatx : SIGNAL is "soleil:user:gtsfp:1.0 GT03 datatx";
ATTRIBUTE X_INTERFACE_INFO of gt03_powergood : SIGNAL is "soleil:user:gtsfp:1.0 GT03 powergood";
ATTRIBUTE X_INTERFACE_INFO of gt03_qplllock : SIGNAL is "soleil:user:gtsfp:1.0 GT03 qplllock";
ATTRIBUTE X_INTERFACE_INFO of gt03_txclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT03 txclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt03_txresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT03 txresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxcdrlock : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxcdrlock";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxbyteisaligned : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxbyteisaligned";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxbyterealign : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxbyterealign";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxcommadet : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxcommadet";
ATTRIBUTE X_INTERFACE_INFO of gt03_txfault : SIGNAL is "soleil:user:gtsfp:1.0 GT03 txfault";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxlos : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxlos";
ATTRIBUTE X_INTERFACE_INFO of gt03_modabs : SIGNAL is "soleil:user:gtsfp:1.0 GT03 modabs";
ATTRIBUTE X_INTERFACE_INFO of gt03_rstall : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rstall";
ATTRIBUTE X_INTERFACE_INFO of gt03_rxcommadeten : SIGNAL is "soleil:user:gtsfp:1.0 GT03 rxcommadeten";
ATTRIBUTE X_INTERFACE_INFO of gt03_txdisable : SIGNAL is "soleil:user:gtsfp:1.0 GT03 txdisable";
ATTRIBUTE X_INTERFACE_INFO of gt04_datarx : SIGNAL is "soleil:user:gtsfp:1.0 GT04 datarx";
ATTRIBUTE X_INTERFACE_INFO of gt04_datatx : SIGNAL is "soleil:user:gtsfp:1.0 GT04 datatx";
ATTRIBUTE X_INTERFACE_INFO of gt04_powergood : SIGNAL is "soleil:user:gtsfp:1.0 GT04 powergood";
ATTRIBUTE X_INTERFACE_INFO of gt04_qplllock : SIGNAL is "soleil:user:gtsfp:1.0 GT04 qplllock";
ATTRIBUTE X_INTERFACE_INFO of gt04_txclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT04 txclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxclkactive";
ATTRIBUTE X_INTERFACE_INFO of gt04_txresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT04 txresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxresetdone";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxcdrlock : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxcdrlock";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxbyteisaligned : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxbyteisaligned";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxbyterealign : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxbyterealign";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxcommadet : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxcommadet";
ATTRIBUTE X_INTERFACE_INFO of gt04_txfault : SIGNAL is "soleil:user:gtsfp:1.0 GT04 txfault"; ATTRIBUTE X_INTERFACE_INFO of gt04_rxlos : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxlos";
ATTRIBUTE X_INTERFACE_INFO of gt04_modabs : SIGNAL is "soleil:user:gtsfp:1.0 GT04 modabs";
ATTRIBUTE X_INTERFACE_INFO of gt04_rstall : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rstall";
ATTRIBUTE X_INTERFACE_INFO of gt04_rxcommadeten : SIGNAL is "soleil:user:gtsfp:1.0 GT04 rxcommadeten";
ATTRIBUTE X_INTERFACE_INFO of gt04_txdisable : SIGNAL is "soleil:user:gtsfp:1.0 GT04 txdisable";
---------------------------
-- COMPONENT DECLARATION --
---------------------------
COMPONENT HTG2QSFP_FMC1_4L_L
PORT (
gtwiz_userclk_tx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
gtrefclk01_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1outclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1outrefclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtyrxn_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
gtyrxp_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rx8b10ben_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rxbufreset_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rxcommadeten_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rxmcommaalignen_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
rxpcommaalignen_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
tx8b10ben_in : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
txctrl0_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
txctrl1_in : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
txctrl2_in : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
gtpowergood_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gtytxn_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
gtytxp_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxbufstatus_out : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
rxbyteisaligned_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxbyterealign_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxclkcorcnt_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rxcommadet_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
rxctrl0_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
rxctrl1_out : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
rxctrl2_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rxctrl3_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
txpmaresetdone_out : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
);
END COMPONENT;
------------------------
-- SIGNAL DECLARATION --
------------------------
signal txclkactive : std_logic;
signal rxclkactive : std_logic;
signal rstall : std_logic; signal txresetdone : std_logic;
signal rxresetdone : std_logic;
signal qplllock : std_logic_vector(1 downto 0);
signal ref_clk : std_logic;
begin
---------------------
-- DIFF CLK BUFFER --
---------------------
ibufd_clkref_inst: IBUFDS_GTE4
generic map (
REFCLK_EN_TX_PATH => '0',
REFCLK_HROW_CK_SEL => "00",
REFCLK_ICNTL_RX => "00"
)
port map (
O => ref_clk,
ODIV2 => open,
CEB => '0',
I => mgtrefclk_p,
IB => mgtrefclk_n
);
--------------------
-- GLOBAL SIGNALS --
--------------------
gt01_txclkactive <= txclkactive;
gt02_txclkactive <= txclkactive;
gt03_txclkactive <= txclkactive;
gt04_txclkactive <= txclkactive;
gt01_rxclkactive <= rxclkactive;
gt02_rxclkactive <= rxclkactive;
gt03_rxclkactive <= rxclkactive;
gt04_rxclkactive <= rxclkactive;
rstall <= gt01_rstall
or gt02_rstall
or gt03_rstall
or gt04_rstall;
gt01_txresetdone <= txresetdone;
gt02_txresetdone <= txresetdone;
gt03_txresetdone <= txresetdone;
gt04_txresetdone <= txresetdone;
gt01_rxresetdone <= rxresetdone;
gt02_rxresetdone <= rxresetdone;
gt03_rxresetdone <= rxresetdone;
gt04_rxresetdone <= rxresetdone;
gt01_qplllock <= qplllock(0);
gt02_qplllock <= qplllock(0);
gt03_qplllock <= qplllock(0);
gt04_qplllock <= qplllock(0);
--------------------------
-- TRANSCEIVER INSTANCE --
--------------------------
gtwiz_inst: HTG2QSFP_FMC1_4L_L
PORT MAP (
gtwiz_userclk_tx_reset_in => "0",
gtwiz_userclk_tx_srcclk_out => open,
gtwiz_userclk_tx_usrclk_out => open,
gtwiz_userclk_tx_usrclk2_out => open,
gtwiz_userclk_tx_active_out(0) => txclkactive, gtwiz_userclk_rx_reset_in => "0",
gtwiz_userclk_rx_srcclk_out => open,
gtwiz_userclk_rx_usrclk_out(0) => usrclk,
gtwiz_userclk_rx_usrclk2_out => open,
gtwiz_userclk_rx_active_out(0) => rxclkactive,
gtwiz_reset_clk_freerun_in(0) => clk_100,
gtwiz_reset_all_in(0) => rstall,
gtwiz_reset_tx_pll_and_datapath_in => "0",
gtwiz_reset_tx_datapath_in => "0",
gtwiz_reset_rx_pll_and_datapath_in => "0",
gtwiz_reset_rx_datapath_in => "0",
gtwiz_reset_rx_cdr_stable_out => open,
gtwiz_reset_tx_done_out(0) => txresetdone,
gtwiz_reset_rx_done_out(0) => rxresetdone,
gtwiz_userdata_tx_in(15 downto 0) => gt01_datatx,
gtwiz_userdata_tx_in(31 downto 16) => gt02_datatx,
gtwiz_userdata_tx_in(47 downto 32) => gt03_datatx,
gtwiz_userdata_tx_in(63 downto 48) => gt04_datatx,
gtwiz_userdata_rx_out(15 downto 0) => gt01_datarx,
gtwiz_userdata_rx_out(31 downto 16) => gt02_datarx,
gtwiz_userdata_rx_out(47 downto 32) => gt03_datarx,
gtwiz_userdata_rx_out(63 downto 48) => gt04_datarx,
gtrefclk01_in(0) => ref_clk,
gtrefclk01_in(1) => ref_clk,
qpll1lock_out => qplllock,
qpll1outclk_out => open,
qpll1outrefclk_out => open,
gtyrxn_in(0) => qsfp01_rx1n,
gtyrxn_in(1) => qsfp01_rx2n,
gtyrxn_in(2) => qsfp01_rx3n,
gtyrxn_in(3) => qsfp01_rx4n,
gtyrxp_in(0) => qsfp01_rx1p,
gtyrxp_in(1) => qsfp01_rx2p,
gtyrxp_in(2) => qsfp01_rx3p,
gtyrxp_in(3) => qsfp01_rx4p,
rxbufreset_in => (others => '0'),
rx8b10ben_in => (others => '1'),
rxcommadeten_in(0) => gt01_rxcommadeten,
rxcommadeten_in(1) => gt02_rxcommadeten,
rxcommadeten_in(2) => gt03_rxcommadeten,
rxcommadeten_in(3) => gt04_rxcommadeten,
rxmcommaalignen_in => (others => '1'),
rxpcommaalignen_in => (others => '1'),
tx8b10ben_in => (others => '1'),
txctrl0_in => (others => '0'),
txctrl1_in => (others => '0'),
txctrl2_in => (others => '0'),
gtpowergood_out(0) => gt01_powergood,
gtpowergood_out(1) => gt02_powergood,
gtpowergood_out(2) => gt03_powergood,
gtpowergood_out(3) => gt04_powergood,
gtytxn_out(0) => qsfp01_tx1n,
gtytxn_out(1) => qsfp01_tx2n,
gtytxn_out(2) => qsfp01_tx3n,
gtytxn_out(3) => qsfp01_tx4n,
gtytxp_out(0) => qsfp01_tx1p,
gtytxp_out(1) => qsfp01_tx2p,
gtytxp_out(2) => qsfp01_tx3p,
gtytxp_out(3) => qsfp01_tx4p,
rxbufstatus_out => open,
rxbyteisaligned_out(0) => gt01_rxbyteisaligned,
rxbyteisaligned_out(1) => gt02_rxbyteisaligned,
rxbyteisaligned_out(2) => gt03_rxbyteisaligned,
rxbyteisaligned_out(3) => gt04_rxbyteisaligned,
rxbyterealign_out(0) => gt01_rxbyterealign,
rxbyterealign_out(1) => gt02_rxbyterealign,
rxbyterealign_out(2) => gt03_rxbyterealign,
rxbyterealign_out(3) => gt04_rxbyterealign,
rxcdrlock_out(0) => gt01_rxcdrlock,
rxcdrlock_out(1) => gt02_rxcdrlock, rxcdrlock_out(2) => gt03_rxcdrlock,
rxcdrlock_out(3) => gt04_rxcdrlock,
rxclkcorcnt_out => open,
rxcommadet_out(0) => gt01_rxcommadet,
rxcommadet_out(1) => gt02_rxcommadet,
rxcommadet_out(2) => gt03_rxcommadet,
rxcommadet_out(3) => gt04_rxcommadet,
rxctrl0_out => open,
rxctrl1_out => open,
rxctrl2_out => open,
rxctrl3_out => open,
rxpmaresetdone_out => open,
txpmaresetdone_out => open
);
----------------------
-- DIRECT CONNEXION --
----------------------
gt01_txfault <= qsfp01_modprsl;
gt02_txfault <= qsfp01_modprsl;
gt03_txfault <= qsfp01_modprsl;
gt04_txfault <= qsfp01_modprsl;
gt01_rxlos <= qsfp01_modprsl;
gt02_rxlos <= qsfp01_modprsl;
gt03_rxlos <= qsfp01_modprsl;
gt04_rxlos <= qsfp01_modprsl;
gt01_modabs <= qsfp01_modprsl;
gt02_modabs <= qsfp01_modprsl;
gt03_modabs <= qsfp01_modprsl;
gt04_modabs <= qsfp01_modprsl;
qsfp01_resetn <= '1';
end architecture rtl;