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BRONES Romain authoredTop level: * Add MC time and PPS port * GT Interface ready combinatorial inside top level Protocol decoder * New GT Interface ready input port * New MC time and PPS input ports * New output ports for new features * Frame counters, frame rates * Sequence checkers * Change output AXIS packet : MC time, packet_time LSB only AXI interface: * Add registers for new features * Fix Makefile rule for RDL->VHD
BRONES Romain authoredTop level: * Add MC time and PPS port * GT Interface ready combinatorial inside top level Protocol decoder * New GT Interface ready input port * New MC time and PPS input ports * New output ports for new features * Frame counters, frame rates * Sequence checkers * Change output AXIS packet : MC time, packet_time LSB only AXI interface: * Add registers for new features * Fix Makefile rule for RDL->VHD
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Makefile 1.56 KiB
###############################################################################
# Global receipes
none:
$(info You should specify what to make: ip, sim, clean, clean-all)
sim:
###############################################################################
# Configuration
hdlpkgsrc :=
###############################################################################
# Generate a source list, depending on the config
rdlsrc := $(shell ls rdl/*.rdl)
rdltarget := $(rdlsrc:rdl/%.rdl=hdl/%.vhd)
hdlsrc := $(shell ls hdl/*.vhd) $(rdltarget) $(hdlpkgsrc)
# TODO: depends on the configuration
tcl/sources.tcl:
echo read_vhdl {$(hdlsrc)} > $@
###############################################################################
# Compute interface from rdl files
hdl/%.vhd:rdl/%.rdl
hectare --axi-vhdl $@ $<
###############################################################################
# Package IP
ip:component.xml
component.xml:tcl/sources.tcl tcl/combpm.tcl tcl/generate_gtwizard.tcl $(hdlsrc)
vivado -mode batch -source tcl/combpm.tcl
###############################################################################
# Synthessize IP for test
synth:component.xml
vivado -mode batch -source tcl/bloc_synthesis.tcl
###############################################################################
# Cleaner Rules
clean:
rm -f vivado*.log vivado*.jou
clean-ip:
rm -rf ip_proj ip_user_files xgui
rm -f component.xml
clean-sim:
rm -f *.wdb
clean-all:clean-ip clean
rm -f tcl/sources.tcl
rm -f hdl/combpm_protocol_electron_ctrl.vhd
.PHONY: clean clean-ip clean-sim clean-all none ip sim synth