Newer
Older
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
= COMBPM module documentation
== Description
This module provides several logic blocks to allow communication with BPM (Beam Position Monitor) electronics.
This has been built for a very precise situation (libera electron, damc-fmc2zup), but the architecture should allow modification and portability.
For now, it only provides RX communication from the DLS CC protocol (ITech libera electron).
The module has been designed for DAMC-FMC2ZUP targets, populated with a 4SFP+ FMC board (CAENels).
== Overview
=== Main operation: Top level
The basics of this module is in three blocs that are essentials for the application.
* *Transceiver bloc*. Used to deserialize the communication stream from the BPM. +
_For now it is a Xilinx GTWizard, configured for the Libera Electron DLS CC protocol specs (2Gbps, 16b words...)._
_This is tied to a specific transceiver input of the FPGA._
* *Protocol decoder bloc*. From the deserialized words, it decode the stream and get the essential data (BPM number, position, timestamp...).
It outputs it on a AXI-Stream interface. +
_For now, it parses Libera Electron DLS CC._
* *AXI-MM register interface*. Used to configure and monitor everything from an AXI-MM interface (CPU).
These three blocs are depicted in the image below.
It is to note that the clock domain used is the data clock, even for the register interface.
This clock is provided and can be used to clock the rest of the application and/or clock CDC on the AXI-MM and AXIS interface. +
_The actual __top_combpm_electron.vhd__ file provides these three blocs configured and connected for the Libera Electron and damc-fmc2zup application._
.Basic overview of combpm module
image::images/overview.svg[]
=== Additionnal blocs
The module provide additionnal blocs usefull for the application.
* Frame filter
== Details
=== BPM frame AXIS stream
The AXIS data provided by the protocol decoder is descibed in the file _pkg_bpmframe_stream.vhd_.
See this file to have up to date fields info.
* Frames are not cut into packets (TLAST always '1').
* No FIFO on output (TREADY is not used).
The application needs to either implement FIFO or accepts every frame (AXIS packet).
The frame rate depends on the signal input.
=== Protocol decoder (electron)
* CRC check. If fails: drop the frame, pulse frame_error output and increase the error counter.
* Counts and gives the number of frame in the last DLS CC sequence receive.
* DLS CC Sequence number check. If discontinuous: pulse seq_discontinuity output and increase
== Future of this module
At SOLEIL, the BPM electronics will change by 2025.
At that point, it will be necessary to change the *Transceivers* and *Protocol decoder* blocs to match the new equipments.
Indicate if the number of frame in the sequence is different from last sequence.