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Commit b4b96ad1 authored by BRONES Romain's avatar BRONES Romain
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feat: Add ComLBP decoding 

* Converge to CCN packeter
parent 4bc74d85
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src/app_fofbnode/hdl/pkg_app_fofb_cellnode.vhd
+ 4
− 4
View file @ b4b96ad1
......@@ -45,10 +45,10 @@ package pkg_app_config is
-- Region 0 is BPM data
constant C_DAQ0_IS_CONTINUOUS : natural := 0;
constant C_DAQ0_MAX_SAMPLES : natural := 16#04000000#; -- Buffer size / 8 bytes
constant C_DAQ0_CHANNELS_IN_TAB : natural := 2;
constant C_DAQ0_MAX_SAMPLES : natural := 16#02000000#; -- Buffer size / 16 bytes
constant C_DAQ0_CHANNELS_IN_TAB : natural := 4;
constant C_DAQ0_TAB_COUNT : natural := 1;
constant C_DAQ0_TAB_CONTENTS : t_natural_vector := (1, 0);
constant C_DAQ0_TAB_CONTENTS : t_natural_vector := (4, 2, 1, 0);
constant C_DAQ0_BUF0_OFFSET : natural := 16#00000000#;
constant C_DAQ0_BUF1_OFFSET : natural := 16#10000000#;
......@@ -57,7 +57,7 @@ package pkg_app_config is
constant C_DAQ1_MAX_SAMPLES : natural := 16#04000000#; -- Buffer size / 8 bytes
constant C_DAQ1_CHANNELS_IN_TAB : natural := 2;
constant C_DAQ1_TAB_COUNT : natural := 1;
constant C_DAQ1_TAB_CONTENTS : t_natural_vector := (3, 2);
constant C_DAQ1_TAB_CONTENTS : t_natural_vector := (4, 3);
constant C_DAQ1_BUF0_OFFSET : natural := 16#20000000#;
constant C_DAQ1_BUF1_OFFSET : natural := 16#30000000#;
......
src/app_fofbnode/hdl/top_app_cellnode.vhd
+ 66
− 81
View file @ b4b96ad1
......@@ -139,12 +139,7 @@ architecture struct of bsp_fmc2zup_payload is
signal axis_pkt_tx_tready : std_logic;
signal axis_pkt_tx_tvalid : std_logic;
signal axis_pkt_tx_tuser : std_logic_vector(7 downto 0);
signal axis_pkt_tx_tdata : std_logic_vector(79 downto 0);
signal axis_pkt_lbp_tready : std_logic;
signal axis_pkt_lbp_tvalid : std_logic;
signal axis_pkt_lbp_tdata : std_logic_vector(31 downto 0);
signal axis_pkt_tx_tdata : std_logic_vector(85 downto 0);
-- PSCGEN
signal axis_pscgen_tdata_value : std_logic_vector(15 downto 0);
......@@ -174,7 +169,7 @@ architecture struct of bsp_fmc2zup_payload is
signal daq_stop : std_logic;
signal daq_trigger : std_logic;
signal r_daq_trigger : std_logic_vector(1 downto 0);
signal daq_data : t_32b_slv_vector(3 downto 0);
signal daq_data : t_32b_slv_vector(4 downto 0);
signal ts_strobe_0 : std_logic_vector(31 downto 0);
signal ts_strobe_1 : std_logic_vector(31 downto 0);
......@@ -439,7 +434,10 @@ begin
-- AXIS output
m_axis_aclk => clk_comlbp,
m_axis_tvalid => axis_comlbp_tvalid,
m_axis_tdata => axis_comlbp_tdata,
m_axis_tdata_xpos => axis_comlbp_tdata_,
m_axis_tdata_ypos => axis_comlbp_tdata_,
m_axis_tdata_faseq => axis_comlbp_tdata_,
m_axis_tdata_bpmid => axis_comlbp_tdata_,
-- AXI-MM interface
s_axi_clk => pi_payload.m_axi4l_reg_aclk,
......@@ -447,75 +445,59 @@ begin
s_axi_s2m => addrmap_i.comlbp_0
);
-------------------
-- UPSTREAM FIFO --
-------------------
-- Throttling and clock domain crossing
inst_upstream_fifo : axis_upstream_fifo
port map (
s_axis_aresetn => pi_payload.m_axi4l_reg_areset_n,
s_axis_aclk => clk_combpm,
s_axis_tvalid => axis_combpm_tvalid,
s_axis_tready => open, -- no back pressure possible on this side
s_axis_tdata => axis_combpm_tdata(79 downto 0),
s_axis_tuser => axis_combpm_tdata(127 downto 120),
m_axis_aclk => pi_payload.m_axi4l_reg_aclk,
m_axis_tvalid => axis_pkt_tx_tvalid,
m_axis_tready => axis_pkt_tx_tready,
m_axis_tdata => axis_pkt_tx_tdata,
m_axis_tuser => axis_pkt_tx_tuser,
almost_full => open -- TODO monitor to detect overrun
);
inst_upstream_lbp_fifo : xpm_fifo_axis
generic map (
CLOCKING_MODE => "independent_clock",
FIFO_DEPTH => 64,
RD_DATA_COUNT_WIDTH => 7,
WR_DATA_COUNT_WIDTH => 7,
RELATED_CLOCKS => 0,
TDATA_WIDTH => 32
)
--------------------------------
-- UPSTREAM AXIS INTERCONNECT --
--------------------------------
inst_rx_axis_ic: entity work.axis_com51_rx
port map (
s_aresetn => pi_payload.m_axi4l_reg_areset_n,
almost_empty_axis => open,
almost_full_axis => open,
dbiterr_axis => open,
sbiterr_axis => open,
prog_empty_axis => open,
prog_full_axis => open,
rd_data_count_axis => open,
wr_data_count_axis => open,
injectdbiterr_axis => '0',
injectsbiterr_axis => '0',
s_aclk => clk_comlbp,
s_axis_tvalid => axis_comlbp_tvalid,
s_axis_tdata => axis_comlbp_tdata,
s_axis_tready => open,
s_axis_tdest => (others => '0'),
s_axis_tid => (others => '0'),
s_axis_tkeep => (others => '0'),
s_axis_tlast => '0',
s_axis_tstrb => (others => '0'),
s_axis_tuser => (others => '0'),
m_aclk => pi_payload.m_axi4l_reg_aclk,
m_axis_tdata => axis_pkt_lbp_tdata,
m_axis_tready => axis_pkt_lbp_tready,
m_axis_tvalid => axis_pkt_lbp_tvalid
--m_axis_tdest => open,
--m_axis_tid => open,
--m_axis_tkeep => open,
--m_axis_tlast => open,
--m_axis_tstrb => open,
--m_axis_tuser => open
aclk => axis_clk,
s00_axis_aclk => clk_combpm,
s01_axis_aclk => clk_comlbp,
s02_axis_aclk => clk_comlbp,
s03_axis_aclk => clk_comlbp,
s04_axis_aclk => clk_comlbp,
m00_axis_aclk => axis_clk,
aresetn => axis_rstn,
s00_axis_aresetn => axis_rstn,
s01_axis_aresetn => axis_rstn,
s02_axis_aresetn => axis_rstn,
s03_axis_aresetn => axis_rstn,
s04_axis_aresetn => axis_rstn,
m00_axis_aresetn => axis_rstn,
s00_axis_tvalid => axis_combpm_tvalid
s00_axis_tready => open,
s00_axis_tdata => x"0" & axis_combpm_tdata(127 downto 120) & axis_combpm_tdata(79 downto 0),
s01_axis_tvalid => axis_comlbp_tvalid,
s01_axis_tready => open,
s01_axis_tdata => axis_comlbp_tdata_faseq & axis_comlbp_tdata_bpmid & axis_comlbp_tdata_posy & axis_comlbp_tdata_posx;
s02_axis_tvalid => '0',
s02_axis_tready => open,
s02_axis_tdata => (others => '0'),
s03_axis_tvalid => '0',
s03_axis_tready => open,
s03_axis_tdata => (others => '0'),
s04_axis_tvalid => '0',
s04_axis_tready => open,
s04_axis_tdata => (others => '0'),
m00_axis_tvalid => axis_pkt_tx_tvalid,
m00_axis_tready => axis_pkt_tx_tready,
m00_axis_tdata => axis_pkt_tx_tdata,
s00_arb_req_suppress => c_std_zero,
s01_arb_req_suppress => c_std_zero,
s02_arb_req_suppress => c_std_zero,
s03_arb_req_suppress => c_std_zero,
s04_arb_req_suppress => c_std_zero
);
-- TEMPORARY !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
axis_pkt_lbp_tready <= '1';
------------------
-- CCN PACKETER --
......@@ -540,8 +522,8 @@ begin
s_axi_s2m => addrmap_i.ccn_packeter_0,
-- AXIS Packet input
s_axis_tdata => axis_pkt_tx_tdata,
s_axis_tuser => axis_pkt_tx_tuser,
s_axis_tdata => axis_pkt_tx_tdata(79 downto 0),
s_axis_tuser => axis_pkt_tx_tdata(88 downto 80), -- fa seq, cropped 8 bits
s_axis_tvalid => axis_pkt_tx_tvalid,
s_axis_tready => axis_pkt_tx_tready,
......@@ -775,13 +757,16 @@ begin
po_payload.s_axi4_daq <= f_common_to_bsp(m_axi4_daq_m2s);
-- Mapping data channel
daq_data(0) <= timeref(31 downto 0);
daq_data(1) <= timeref(63 downto 32);
daq_data(2) <= timeref(31 downto 0);
daq_data(3) <= timeref(63 downto 32);
daq_data(0) <= axis_pkt_tx_tdata(31 downto 0);
daq_data(1) <= axis_pkt_tx_tdata(63 downto 32);
daq_data(2) <= axis_pkt_tx_tdata(95 downto 64);
daq_data(3)(15 downto 0) <= axis_comcorr_tdata(31 downto 16);
daq_data(3)(23 downto 16) <= axis_comcorr_tdata(7 downto 0);
daq_data(3)(31 downto 24) <= axis_comcorr_tuser(7 downto 0);
daq_data(4) <= timeref(31 downto 0);
daq_strobe(0) <= axis_pkt_tx_tvalid and axis_pkt_tx_tready;
daq_strobe(1) <= axis_pkt_lbp_tvalid and axis_pkt_lbp_tready;
daq_strobe(1) <= axis_comcorr_tvalid;
daq_stop <= addrmap_o.daq_control.stop.data(0);
......
src/app_fofbnode/tcl/gen_ip_cellnode.tcl
+ 54
− 0
View file @ b4b96ad1
......@@ -25,3 +25,57 @@ generate_target all [get_files ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipN
export_ip_user_files -of_objects [get_files ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci]
## ------------------------------------- ##
## UPSTREAM INTERCONNECT
## ------------------------------------- ##
set ipName "axis_com51_rx"
# 5 to 1 axis interconnect for bpm/lpb reception
set xcipath [create_ip \
-name axis_interconnect \
-vendor xilinx.com \
-library ip -version 1.1 \
-module_name $ipName]
set_property -dict [list \
CONFIG.C_NUM_SI_SLOTS {5} \
CONFIG.SWITCH_TDATA_NUM_BYTES {12} \
CONFIG.HAS_TSTRB {false} \
CONFIG.HAS_TKEEP {false} \
CONFIG.HAS_TLAST {false} \
CONFIG.HAS_TID {false} \
CONFIG.HAS_TDEST {false} \
CONFIG.HAS_TUSER {false} \
CONFIG.SWITCH_TUSER_BITS_PER_BYTE {1} \
CONFIG.ARBITER_TYPE {Fixed} \
CONFIG.S00_AXIS_FIFO_MODE {1_(Normal)} \
CONFIG.C_S00_AXIS_FIFO_DEPTH {64} \
CONFIG.S01_AXIS_FIFO_MODE {1_(Normal)} \
CONFIG.C_S01_AXIS_FIFO_DEPTH {64} \
CONFIG.S02_AXIS_FIFO_MODE {1_(Normal)} \
CONFIG.C_S02_AXIS_FIFO_DEPTH {64} \
CONFIG.S03_AXIS_FIFO_MODE {1_(Normal)} \
CONFIG.C_S03_AXIS_FIFO_DEPTH {64} \
CONFIG.S04_AXIS_FIFO_MODE {1_(Normal)} \
CONFIG.C_S04_AXIS_FIFO_DEPTH {64} \
CONFIG.SWITCH_PACKET_MODE {false} \
CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {1} \
CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} \
CONFIG.M00_AXIS_TDATA_NUM_BYTES {12} \
CONFIG.S00_AXIS_TDATA_NUM_BYTES {12} \
CONFIG.S01_AXIS_TDATA_NUM_BYTES {12} \
CONFIG.S02_AXIS_TDATA_NUM_BYTES {12} \
CONFIG.S03_AXIS_TDATA_NUM_BYTES {12} \
CONFIG.S04_AXIS_TDATA_NUM_BYTES {12} \
CONFIG.M00_S01_CONNECTIVITY {true} \
CONFIG.M00_S02_CONNECTIVITY {true} \
CONFIG.M00_S03_CONNECTIVITY {true} \
CONFIG.M00_S04_CONNECTIVITY {true} \
] [get_ips $ipName]
generate_target all [get_files ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci]
export_ip_user_files -of_objects [get_files ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci]
comlbp @ cdd2c390
Compare 8a4a68f2...cdd2c390
Subproject commit 8a4a68f22b6d8c421733d82dc4c40d331bca7af8
Subproject commit cdd2c390bbeb21ded653271d6dd0ced85f399be4
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