Skip to content
Snippets Groups Projects
Commit 7b721f7d authored by BRONES Romain's avatar BRONES Romain
Browse files

Merge developments 

Major change
* Adding COMLBP
    * Integration of another 4SFP+ FMC
    * Adding four COMLBP modules on this FMC
    * Add interconnect to aggregate COMBPM and COMLBP data

Minor changes
* COMBPM: add a sequence offset register
* CORRMATRIX: increase bpmid width to count up to 255
* CellNode DAQ data ingest has been changed
* Keeping up to date with fwk
* Reject update of lib, DAS stream declaration
parents fdf65a9a e636e010
No related branches found
No related tags found
No related merge requests found
Expand all Show whitespace changes
Inline Side-by-side
Showing
with 2204 additions and 1349 deletions
.gitmodules
+ 6
− 3
View file @ 7b721f7d
[submodule "fwk"] [submodule "fwk"]
path = fwk path = fwk
url = git@gitlab.desy.de:fpgafw/fwk.git url = https://gitlab.desy.de/fpgafw/fwk.git
branch = main branch = main
[submodule "src/fmc_4sfp"] [submodule "src/fmc_4sfp"]
path = src/fmc_4sfp path = src/fmc_4sfp
...@@ -30,14 +30,14 @@ ...@@ -30,14 +30,14 @@
url = git@gitlab.synchrotron-soleil.fr:dg/fofb/comcorr.git url = git@gitlab.synchrotron-soleil.fr:dg/fofb/comcorr.git
[submodule "src/bsp_msk"] [submodule "src/bsp_msk"]
path = src/bsp_msk path = src/bsp_msk
url = git@gitlab.desy.de:fpgafw/mod/bsp/bsp_fmc2zup.git url = https://gitlab.desy.de/fpgafw/mod/bsp/bsp_fmc2zup.git
branch = dev-soleil-rbt branch = dev-soleil-rbt
[submodule "src/pscgen"] [submodule "src/pscgen"]
path = src/pscgen path = src/pscgen
url = git@gitlab.synchrotron-soleil.fr:dg/fofb/pscgen.git url = git@gitlab.synchrotron-soleil.fr:dg/fofb/pscgen.git
[submodule "src/lib/desy_vhdl"] [submodule "src/lib/desy_vhdl"]
path = src/lib/desy_vhdl path = src/lib/desy_vhdl
url = git@gitlab.desy.de:fpgafw/lib/desy_vhdl.git url = https://gitlab.desy.de/fpgafw/lib/desy_vhdl.git
branch = main branch = main
[submodule "src/daq"] [submodule "src/daq"]
path = src/daq path = src/daq
...@@ -45,3 +45,6 @@ ...@@ -45,3 +45,6 @@
[submodule "src/corr_matrixpi"] [submodule "src/corr_matrixpi"]
path = src/corr_matrix path = src/corr_matrix
url = git@gitlab.synchrotron-soleil.fr:dg/fofb/corr_matrixpi.git url = git@gitlab.synchrotron-soleil.fr:dg/fofb/corr_matrixpi.git
[submodule "src/comlbp"]
path = src/comlbp
url = https://gitlab.synchrotron-soleil.fr/dg/fofb/comlbp.git
LICENSE 0 → 100644
+ 674
− 0
View file @ 7b721f7d
This diff is collapsed.
README.adoc 0 → 100644
+ 7
− 0
View file @ 7b721f7d
// Referencing the true README inside the modules.
// This README on the front page just includes it.
:imagesdir: doc/images
include::doc/main.adoc[]
doc/images/synoptique_application_blocsdetailled.png 0 → 100644
+ 0
− 0
View file @ 7b721f7d
doc/images/synoptique_application_blocsdetailled.png

62.4 KiB

doc/images/synoptique_application_topo.png 0 → 100644
+ 0
− 0
View file @ 7b721f7d
doc/images/synoptique_application_topo.png

91.7 KiB

doc/images/synoptique_platform.png 0 → 100644
+ 0
− 0
View file @ 7b721f7d
doc/images/synoptique_platform.png

80.4 KiB

doc/main.adoc
+ 107
− 1
View file @ 7b721f7d
= Documentation = FOFB Node Documentation
// ================================================================================
== Description
This FWK project is used to build the two configuration of FOFBNodes : CellNode and CentralNode.
The target system is a DAMC-FMC2ZUP board with a FMC-4SFP+ equiped.
The next figure gives a global idea of the Fofb Nodes integration to SOLEIL Fast Orbit Feedback.
Beam Position Monitors (BPM) output the position data, and Power Supply Controller (PSC) drive the steering magnets to move the beam with the correction values.
image::synoptique_application_topo.png[Topology,350]
// ================================================================================
== Overview
The built firmware will sit in the PL (FPGA) part of a Xilinx SoC.
image::synoptique_platform.png[Platform,500]
Details of the processing blocs are given in the next figure.
image::synoptique_application_blocsdetailled.png[Detailed Application Blocs, 500]
=== Modules used
|===
| FMC2ZUP BSP (desy msk) | BSP for the main board
| FMC4-SFP interface | Simple interface layer
| DAQ (desy msk) | DAQ used to record data and forward in on board DDR
| CCN Ethernet | Communication CellNodes, transmit and receive ethernet frames from/to AXI-Stream
| CCN Packet | Communication CellNodes, packeter and unpacketer for the frames
| COMBPM | (CellNode only) Receive frames from BPMs, filter and put packets on a AXI-Stream
| COMCORR | (CellNode only) Transmit frames to PSC
| CORR Matrix | (CentralNode only) Compute correction from BPM position data
| DESY LIB (desy msk) | Several basic components and interfaces
|===
// ================================================================================
== Generation
=== System requirements
* Vivado version targeted : Vivado 2020.2.
The TCL interpreter shall be accessible in the environment PATH.
(Use the script `settings64.sh` provided by Xilinx)
* Python3.8 shall be installed with venv
=== Building firmware
==== Checking out the source code
git clone git@gitlab.synchrotron-soleil.fr:dg/fofb/cellnode_fpga.git prod_fofbnode
cd prod_fofbnode/
git submodule update --init --recursive
==== Quick tour
Taking a look in the checked out files, we can see the different modules used in the `src` directory.
FWK will use information set in the different `.cfg` and `.tcl` files.
├── cfg
│ ├── cellnode.cfg
│ ├── centralnode.cfg
│ └── default.cfg
├── doc
├── fwk
├── Makefile
├── README.adoc
├── src
│ ├── app_fofbnode
│ ├── bsp_msk
│ ├── ccn_packet
│ ├── combpm
│ ├── comcellnode_ethernet
│ ├── comcorr
│ ├── corr_matrix
│ ├── daq
│ ├── fmc_4sfp
│ ├── lib
│ └── pscgen
└── tcl
└── project.tcl
==== Building
The build process is handled by FWK makefile.
Install dependency in a local environment (fwk).
This is required only once.
make env
Create the project then build it, for both configurations (default is CellNode)
make project && make project cfg=centralnode
make build && make build cfg=centralnode
==== Getting output files
All output files are located in the `out` directory.
`.xsa` and `.mapt` files are then to be forwarded to the YOCTO build system: https://gitlab.synchrotron-soleil.fr/dg/fofb/fofb-yocto
\ No newline at end of file
fwk @ 1275eaec
Subproject commit 53ebc93b97b6c66872b09e698b50eb10e03caec7 Subproject commit 1275eaecb355d433b4ec2a15133ee394def68b56
src/app_fofbnode/hdl/combpm_gtwizard_gthe4_common_wrapper.v
+ 172
− 297
View file @ 7b721f7d
This diff is collapsed.
src/app_fofbnode/hdl/comlbp_gtwizard_gtye4_common_wrapper.v 0 → 100644
+ 312
− 0
View file @ 7b721f7d
`timescale 1ps/1ps
module comlbp_gtwizard_gtye4_common_wrapper (
input wire [ 0:0] GTYE4_COMMON_BGBYPASSB,
input wire [ 0:0] GTYE4_COMMON_BGMONITORENB,
input wire [ 0:0] GTYE4_COMMON_BGPDB,
input wire [ 4:0] GTYE4_COMMON_BGRCALOVRD,
input wire [ 0:0] GTYE4_COMMON_BGRCALOVRDENB,
input wire [15:0] GTYE4_COMMON_DRPADDR,
input wire [ 0:0] GTYE4_COMMON_DRPCLK,
input wire [15:0] GTYE4_COMMON_DRPDI,
input wire [ 0:0] GTYE4_COMMON_DRPEN,
input wire [ 0:0] GTYE4_COMMON_DRPWE,
input wire [ 0:0] GTYE4_COMMON_GTGREFCLK0,
input wire [ 0:0] GTYE4_COMMON_GTGREFCLK1,
input wire [ 0:0] GTYE4_COMMON_GTNORTHREFCLK00,
input wire [ 0:0] GTYE4_COMMON_GTNORTHREFCLK01,
input wire [ 0:0] GTYE4_COMMON_GTNORTHREFCLK10,
input wire [ 0:0] GTYE4_COMMON_GTNORTHREFCLK11,
input wire [ 0:0] GTYE4_COMMON_GTREFCLK00,
input wire [ 0:0] GTYE4_COMMON_GTREFCLK01,
input wire [ 0:0] GTYE4_COMMON_GTREFCLK10,
input wire [ 0:0] GTYE4_COMMON_GTREFCLK11,
input wire [ 0:0] GTYE4_COMMON_GTSOUTHREFCLK00,
input wire [ 0:0] GTYE4_COMMON_GTSOUTHREFCLK01,
input wire [ 0:0] GTYE4_COMMON_GTSOUTHREFCLK10,
input wire [ 0:0] GTYE4_COMMON_GTSOUTHREFCLK11,
input wire [ 2:0] GTYE4_COMMON_PCIERATEQPLL0,
input wire [ 2:0] GTYE4_COMMON_PCIERATEQPLL1,
input wire [ 7:0] GTYE4_COMMON_PMARSVD0,
input wire [ 7:0] GTYE4_COMMON_PMARSVD1,
input wire [ 0:0] GTYE4_COMMON_QPLL0CLKRSVD0,
input wire [ 0:0] GTYE4_COMMON_QPLL0CLKRSVD1,
input wire [ 7:0] GTYE4_COMMON_QPLL0FBDIV,
input wire [ 0:0] GTYE4_COMMON_QPLL0LOCKDETCLK,
input wire [ 0:0] GTYE4_COMMON_QPLL0LOCKEN,
input wire [ 0:0] GTYE4_COMMON_QPLL0PD,
input wire [ 2:0] GTYE4_COMMON_QPLL0REFCLKSEL,
input wire [ 0:0] GTYE4_COMMON_QPLL0RESET,
input wire [ 0:0] GTYE4_COMMON_QPLL1CLKRSVD0,
input wire [ 0:0] GTYE4_COMMON_QPLL1CLKRSVD1,
input wire [ 7:0] GTYE4_COMMON_QPLL1FBDIV,
input wire [ 0:0] GTYE4_COMMON_QPLL1LOCKDETCLK,
input wire [ 0:0] GTYE4_COMMON_QPLL1LOCKEN,
input wire [ 0:0] GTYE4_COMMON_QPLL1PD,
input wire [ 2:0] GTYE4_COMMON_QPLL1REFCLKSEL,
input wire [ 0:0] GTYE4_COMMON_QPLL1RESET,
input wire [ 7:0] GTYE4_COMMON_QPLLRSVD1,
input wire [ 4:0] GTYE4_COMMON_QPLLRSVD2,
input wire [ 4:0] GTYE4_COMMON_QPLLRSVD3,
input wire [ 7:0] GTYE4_COMMON_QPLLRSVD4,
input wire [ 0:0] GTYE4_COMMON_RCALENB,
input wire [24:0] GTYE4_COMMON_SDM0DATA,
input wire [ 0:0] GTYE4_COMMON_SDM0RESET,
input wire [ 0:0] GTYE4_COMMON_SDM0TOGGLE,
input wire [ 1:0] GTYE4_COMMON_SDM0WIDTH,
input wire [24:0] GTYE4_COMMON_SDM1DATA,
input wire [ 0:0] GTYE4_COMMON_SDM1RESET,
input wire [ 0:0] GTYE4_COMMON_SDM1TOGGLE,
input wire [ 1:0] GTYE4_COMMON_SDM1WIDTH,
input wire [ 0:0] GTYE4_COMMON_UBCFGSTREAMEN,
input wire [15:0] GTYE4_COMMON_UBDO,
input wire [ 0:0] GTYE4_COMMON_UBDRDY,
input wire [ 0:0] GTYE4_COMMON_UBENABLE,
input wire [ 1:0] GTYE4_COMMON_UBGPI,
input wire [ 1:0] GTYE4_COMMON_UBINTR,
input wire [ 0:0] GTYE4_COMMON_UBIOLMBRST,
input wire [ 0:0] GTYE4_COMMON_UBMBRST,
input wire [ 0:0] GTYE4_COMMON_UBMDMCAPTURE,
input wire [ 0:0] GTYE4_COMMON_UBMDMDBGRST,
input wire [ 0:0] GTYE4_COMMON_UBMDMDBGUPDATE,
input wire [ 3:0] GTYE4_COMMON_UBMDMREGEN,
input wire [ 0:0] GTYE4_COMMON_UBMDMSHIFT,
input wire [ 0:0] GTYE4_COMMON_UBMDMSYSRST,
input wire [ 0:0] GTYE4_COMMON_UBMDMTCK,
input wire [ 0:0] GTYE4_COMMON_UBMDMTDI,
output wire [15:0] GTYE4_COMMON_DRPDO,
output wire [ 0:0] GTYE4_COMMON_DRPRDY,
output wire [ 7:0] GTYE4_COMMON_PMARSVDOUT0,
output wire [ 7:0] GTYE4_COMMON_PMARSVDOUT1,
output wire [ 0:0] GTYE4_COMMON_QPLL0FBCLKLOST,
output wire [ 0:0] GTYE4_COMMON_QPLL0LOCK,
output wire [ 0:0] GTYE4_COMMON_QPLL0OUTCLK,
output wire [ 0:0] GTYE4_COMMON_QPLL0OUTREFCLK,
output wire [ 0:0] GTYE4_COMMON_QPLL0REFCLKLOST,
output wire [ 0:0] GTYE4_COMMON_QPLL1FBCLKLOST,
output wire [ 0:0] GTYE4_COMMON_QPLL1LOCK,
output wire [ 0:0] GTYE4_COMMON_QPLL1OUTCLK,
output wire [ 0:0] GTYE4_COMMON_QPLL1OUTREFCLK,
output wire [ 0:0] GTYE4_COMMON_QPLL1REFCLKLOST,
output wire [ 7:0] GTYE4_COMMON_QPLLDMONITOR0,
output wire [ 7:0] GTYE4_COMMON_QPLLDMONITOR1,
output wire [ 0:0] GTYE4_COMMON_REFCLKOUTMONITOR0,
output wire [ 0:0] GTYE4_COMMON_REFCLKOUTMONITOR1,
output wire [ 1:0] GTYE4_COMMON_RXRECCLK0SEL,
output wire [ 1:0] GTYE4_COMMON_RXRECCLK1SEL,
output wire [ 3:0] GTYE4_COMMON_SDM0FINALOUT,
output wire [14:0] GTYE4_COMMON_SDM0TESTDATA,
output wire [ 3:0] GTYE4_COMMON_SDM1FINALOUT,
output wire [14:0] GTYE4_COMMON_SDM1TESTDATA,
output wire [15:0] GTYE4_COMMON_UBDADDR,
output wire [ 0:0] GTYE4_COMMON_UBDEN,
output wire [15:0] GTYE4_COMMON_UBDI,
output wire [ 0:0] GTYE4_COMMON_UBDWE,
output wire [ 0:0] GTYE4_COMMON_UBMDMTDO,
output wire [ 0:0] GTYE4_COMMON_UBRSVDOUT,
output wire [ 0:0] GTYE4_COMMON_UBTXUART
);
GTYE4_COMMON #(
.AEN_QPLL0_FBDIV (1'b1),
.AEN_QPLL1_FBDIV (1'b1),
.AEN_SDM0TOGGLE (1'b0),
.AEN_SDM1TOGGLE (1'b0),
.A_SDM0TOGGLE (1'b0),
.A_SDM1DATA_HIGH (9'b000000000),
.A_SDM1DATA_LOW (16'b0000000000000000),
.A_SDM1TOGGLE (1'b0),
.BIAS_CFG0 (16'b0000000000000000),
.BIAS_CFG1 (16'b0000000000000000),
.BIAS_CFG2 (16'b0000000100100100),
.BIAS_CFG3 (16'b0000000001000001),
.BIAS_CFG4 (16'b0000000000010000),
.BIAS_CFG_RSVD (16'b0000000000000000),
.COMMON_CFG0 (16'b0000000000000000),
.COMMON_CFG1 (16'b0000000000000000),
.POR_CFG (16'b0000000000000000),
.PPF0_CFG (16'b0000011000000000),
.PPF1_CFG (16'b0000100100000000),
.QPLL0CLKOUT_RATE ("HALF"),
.QPLL0_CFG0 (16'b0011001100011100),
.QPLL0_CFG1 (16'b1101000000111000),
.QPLL0_CFG1_G3 (16'b1101000000111000),
.QPLL0_CFG2 (16'b0000111111000000),
.QPLL0_CFG2_G3 (16'b0000111111000000),
.QPLL0_CFG3 (16'b0000000100100000),
.QPLL0_CFG4 (16'b0000000000000010),
.QPLL0_CP (10'b0011111111),
.QPLL0_CP_G3 (10'b0000001111),
.QPLL0_FBDIV (66),
.QPLL0_FBDIV_G3 (160),
.QPLL0_INIT_CFG0 (16'b0000001010110010),
.QPLL0_INIT_CFG1 (8'b00000000),
.QPLL0_LOCK_CFG (16'b0010010111101000),
.QPLL0_LOCK_CFG_G3 (16'b0010010111101000),
.QPLL0_LPF (10'b1000111111),
.QPLL0_LPF_G3 (10'b0111010101),
.QPLL0_PCI_EN (1'b0),
.QPLL0_RATE_SW_USE_DRP (1'b1),
.QPLL0_REFCLK_DIV (1),
.QPLL0_SDM_CFG0 (16'b0000000010000000),
.QPLL0_SDM_CFG1 (16'b0000000000000000),
.QPLL0_SDM_CFG2 (16'b0000000000000000),
.QPLL1CLKOUT_RATE ("HALF"),
.QPLL1_CFG0 (16'b0011001100011100),
.QPLL1_CFG1 (16'b1101000000111000),
.QPLL1_CFG1_G3 (16'b1101000000111000),
.QPLL1_CFG2 (16'b0000111111000000),
.QPLL1_CFG2_G3 (16'b0000111111000000),
.QPLL1_CFG3 (16'b0000000100100000),
.QPLL1_CFG4 (16'b0000000000000010),
.QPLL1_CP (10'b0011111111),
.QPLL1_CP_G3 (10'b0001111111),
.QPLL1_FBDIV (83),
.QPLL1_FBDIV_G3 (80),
.QPLL1_INIT_CFG0 (16'b0000001010110010),
.QPLL1_INIT_CFG1 (8'b00000000),
.QPLL1_LOCK_CFG (16'b0010010111101000),
.QPLL1_LOCK_CFG_G3 (16'b0010010111101000),
.QPLL1_LPF (10'b1100111111),
.QPLL1_LPF_G3 (10'b0111010100),
.QPLL1_PCI_EN (1'b0),
.QPLL1_RATE_SW_USE_DRP (1'b1),
.QPLL1_REFCLK_DIV (1),
.QPLL1_SDM_CFG0 (16'b0000000000000000),
.QPLL1_SDM_CFG1 (16'b0000000000000000),
.QPLL1_SDM_CFG2 (16'b0000000000000000),
.RSVD_ATTR0 (16'b0000000000000000),
.RSVD_ATTR1 (16'b0000000000000000),
.RSVD_ATTR2 (16'b0000000000000000),
.RSVD_ATTR3 (16'b0000000000000000),
.RXRECCLKOUT0_SEL (2'b00),
.RXRECCLKOUT1_SEL (2'b00),
.SARC_ENB (1'b0),
.SARC_SEL (1'b0),
.SDM0INITSEED0_0 (16'b0000000100010001),
.SDM0INITSEED0_1 (9'b000010001),
.SDM1INITSEED0_0 (16'b0000000100010001),
.SDM1INITSEED0_1 (9'b000010001),
.SIM_MODE ("FAST"),
.SIM_RESET_SPEEDUP ("TRUE"),
.SIM_DEVICE ("ULTRASCALE_PLUS"),
.UB_CFG0 (16'b0000000000000000),
.UB_CFG1 (16'b0000000000000000),
.UB_CFG2 (16'b0000000000000000),
.UB_CFG3 (16'b0000000000000000),
.UB_CFG4 (16'b0000000000000000),
.UB_CFG5 (16'b0000010000000000),
.UB_CFG6 (16'b0000000000000000)
) GTYE4_COMMON_PRIM_INST (
.BGBYPASSB (GTYE4_COMMON_BGBYPASSB),
.BGMONITORENB (GTYE4_COMMON_BGMONITORENB),
.BGPDB (GTYE4_COMMON_BGPDB),
.BGRCALOVRD (GTYE4_COMMON_BGRCALOVRD),
.BGRCALOVRDENB (GTYE4_COMMON_BGRCALOVRDENB),
.DRPADDR (GTYE4_COMMON_DRPADDR),
.DRPCLK (GTYE4_COMMON_DRPCLK),
.DRPDI (GTYE4_COMMON_DRPDI),
.DRPEN (GTYE4_COMMON_DRPEN),
.DRPWE (GTYE4_COMMON_DRPWE),
.GTGREFCLK0 (GTYE4_COMMON_GTGREFCLK0),
.GTGREFCLK1 (GTYE4_COMMON_GTGREFCLK1),
.GTNORTHREFCLK00 (GTYE4_COMMON_GTNORTHREFCLK00),
.GTNORTHREFCLK01 (GTYE4_COMMON_GTNORTHREFCLK01),
.GTNORTHREFCLK10 (GTYE4_COMMON_GTNORTHREFCLK10),
.GTNORTHREFCLK11 (GTYE4_COMMON_GTNORTHREFCLK11),
.GTREFCLK00 (GTYE4_COMMON_GTREFCLK00),
.GTREFCLK01 (GTYE4_COMMON_GTREFCLK01),
.GTREFCLK10 (GTYE4_COMMON_GTREFCLK10),
.GTREFCLK11 (GTYE4_COMMON_GTREFCLK11),
.GTSOUTHREFCLK00 (GTYE4_COMMON_GTSOUTHREFCLK00),
.GTSOUTHREFCLK01 (GTYE4_COMMON_GTSOUTHREFCLK01),
.GTSOUTHREFCLK10 (GTYE4_COMMON_GTSOUTHREFCLK10),
.GTSOUTHREFCLK11 (GTYE4_COMMON_GTSOUTHREFCLK11),
.PCIERATEQPLL0 (GTYE4_COMMON_PCIERATEQPLL0),
.PCIERATEQPLL1 (GTYE4_COMMON_PCIERATEQPLL1),
.PMARSVD0 (GTYE4_COMMON_PMARSVD0),
.PMARSVD1 (GTYE4_COMMON_PMARSVD1),
.QPLL0CLKRSVD0 (GTYE4_COMMON_QPLL0CLKRSVD0),
.QPLL0CLKRSVD1 (GTYE4_COMMON_QPLL0CLKRSVD1),
.QPLL0FBDIV (GTYE4_COMMON_QPLL0FBDIV),
.QPLL0LOCKDETCLK (GTYE4_COMMON_QPLL0LOCKDETCLK),
.QPLL0LOCKEN (GTYE4_COMMON_QPLL0LOCKEN),
.QPLL0PD (GTYE4_COMMON_QPLL0PD),
.QPLL0REFCLKSEL (GTYE4_COMMON_QPLL0REFCLKSEL),
.QPLL0RESET (GTYE4_COMMON_QPLL0RESET),
.QPLL1CLKRSVD0 (GTYE4_COMMON_QPLL1CLKRSVD0),
.QPLL1CLKRSVD1 (GTYE4_COMMON_QPLL1CLKRSVD1),
.QPLL1FBDIV (GTYE4_COMMON_QPLL1FBDIV),
.QPLL1LOCKDETCLK (GTYE4_COMMON_QPLL1LOCKDETCLK),
.QPLL1LOCKEN (GTYE4_COMMON_QPLL1LOCKEN),
.QPLL1PD (GTYE4_COMMON_QPLL1PD),
.QPLL1REFCLKSEL (GTYE4_COMMON_QPLL1REFCLKSEL),
.QPLL1RESET (GTYE4_COMMON_QPLL1RESET),
.QPLLRSVD1 (GTYE4_COMMON_QPLLRSVD1),
.QPLLRSVD2 (GTYE4_COMMON_QPLLRSVD2),
.QPLLRSVD3 (GTYE4_COMMON_QPLLRSVD3),
.QPLLRSVD4 (GTYE4_COMMON_QPLLRSVD4),
.RCALENB (GTYE4_COMMON_RCALENB),
.SDM0DATA (GTYE4_COMMON_SDM0DATA),
.SDM0RESET (GTYE4_COMMON_SDM0RESET),
.SDM0TOGGLE (GTYE4_COMMON_SDM0TOGGLE),
.SDM0WIDTH (GTYE4_COMMON_SDM0WIDTH),
.SDM1DATA (GTYE4_COMMON_SDM1DATA),
.SDM1RESET (GTYE4_COMMON_SDM1RESET),
.SDM1TOGGLE (GTYE4_COMMON_SDM1TOGGLE),
.SDM1WIDTH (GTYE4_COMMON_SDM1WIDTH),
.UBCFGSTREAMEN (GTYE4_COMMON_UBCFGSTREAMEN),
.UBDO (GTYE4_COMMON_UBDO),
.UBDRDY (GTYE4_COMMON_UBDRDY),
.UBENABLE (GTYE4_COMMON_UBENABLE),
.UBGPI (GTYE4_COMMON_UBGPI),
.UBINTR (GTYE4_COMMON_UBINTR),
.UBIOLMBRST (GTYE4_COMMON_UBIOLMBRST),
.UBMBRST (GTYE4_COMMON_UBMBRST),
.UBMDMCAPTURE (GTYE4_COMMON_UBMDMCAPTURE),
.UBMDMDBGRST (GTYE4_COMMON_UBMDMDBGRST),
.UBMDMDBGUPDATE (GTYE4_COMMON_UBMDMDBGUPDATE),
.UBMDMREGEN (GTYE4_COMMON_UBMDMREGEN),
.UBMDMSHIFT (GTYE4_COMMON_UBMDMSHIFT),
.UBMDMSYSRST (GTYE4_COMMON_UBMDMSYSRST),
.UBMDMTCK (GTYE4_COMMON_UBMDMTCK),
.UBMDMTDI (GTYE4_COMMON_UBMDMTDI),
.DRPDO (GTYE4_COMMON_DRPDO),
.DRPRDY (GTYE4_COMMON_DRPRDY),
.PMARSVDOUT0 (GTYE4_COMMON_PMARSVDOUT0),
.PMARSVDOUT1 (GTYE4_COMMON_PMARSVDOUT1),
.QPLL0FBCLKLOST (GTYE4_COMMON_QPLL0FBCLKLOST),
.QPLL0LOCK (GTYE4_COMMON_QPLL0LOCK),
.QPLL0OUTCLK (GTYE4_COMMON_QPLL0OUTCLK),
.QPLL0OUTREFCLK (GTYE4_COMMON_QPLL0OUTREFCLK),
.QPLL0REFCLKLOST (GTYE4_COMMON_QPLL0REFCLKLOST),
.QPLL1FBCLKLOST (GTYE4_COMMON_QPLL1FBCLKLOST),
.QPLL1LOCK (GTYE4_COMMON_QPLL1LOCK),
.QPLL1OUTCLK (GTYE4_COMMON_QPLL1OUTCLK),
.QPLL1OUTREFCLK (GTYE4_COMMON_QPLL1OUTREFCLK),
.QPLL1REFCLKLOST (GTYE4_COMMON_QPLL1REFCLKLOST),
.QPLLDMONITOR0 (GTYE4_COMMON_QPLLDMONITOR0),
.QPLLDMONITOR1 (GTYE4_COMMON_QPLLDMONITOR1),
.REFCLKOUTMONITOR0 (GTYE4_COMMON_REFCLKOUTMONITOR0),
.REFCLKOUTMONITOR1 (GTYE4_COMMON_REFCLKOUTMONITOR1),
.RXRECCLK0SEL (GTYE4_COMMON_RXRECCLK0SEL),
.RXRECCLK1SEL (GTYE4_COMMON_RXRECCLK1SEL),
.SDM0FINALOUT (GTYE4_COMMON_SDM0FINALOUT),
.SDM0TESTDATA (GTYE4_COMMON_SDM0TESTDATA),
.SDM1FINALOUT (GTYE4_COMMON_SDM1FINALOUT),
.SDM1TESTDATA (GTYE4_COMMON_SDM1TESTDATA),
.UBDADDR (GTYE4_COMMON_UBDADDR),
.UBDEN (GTYE4_COMMON_UBDEN),
.UBDI (GTYE4_COMMON_UBDI),
.UBDWE (GTYE4_COMMON_UBDWE),
.UBMDMTDO (GTYE4_COMMON_UBMDMTDO),
.UBRSVDOUT (GTYE4_COMMON_UBRSVDOUT),
.UBTXUART (GTYE4_COMMON_UBTXUART)
);
endmodule
src/app_fofbnode/hdl/gtwizard_ultrascale_v1_7_gthe4_common.v deleted 100644 → 0
+ 0
− 928
View file @ fdf65a9a
This diff is collapsed.
src/app_fofbnode/hdl/gtye_common.vhd 0 → 100755
+ 296
− 0
View file @ 7b721f7d
library ieee;
use ieee.std_logic_1164.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity gtye_common is
port(
-- Differential clock intput
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
-- Detection features
freerun_clk : in std_logic;
-- Buffered ref
buff_gtrefclk : out std_logic;
-- QPLL0 interface
qpll0reset : in std_logic;
qpll0lock : out std_logic;
qpll0outclk : out std_logic;
qpll0refclk : out std_logic;
qpll0fblost : out std_logic;
qpll0reflost : out std_logic;
-- QPLL0 interface
qpll1reset : in std_logic;
qpll1lock : out std_logic;
qpll1outclk : out std_logic;
qpll1refclk : out std_logic;
qpll1fblost : out std_logic;
qpll1reflost : out std_logic
);
end entity gtye_common;
architecture struct of gtye_common is
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO of gtrefclk_p: SIGNAL is "xilinx.com:interface:diff_clock:1.0 gtrefclk_diff CLK_P";
ATTRIBUTE X_INTERFACE_INFO of gtrefclk_n: SIGNAL is "xilinx.com:interface:diff_clock:1.0 gtrefclk_diff CLK_N";
signal gtrefclk : std_logic;
signal gtrefclk_out2 : std_logic;
component comlbp_gtwizard_gtye4_common_wrapper
port(
GTYE4_COMMON_BGBYPASSB : in std_logic_vector(0 downto 0);
GTYE4_COMMON_BGMONITORENB : in std_logic_vector(0 downto 0);
GTYE4_COMMON_BGPDB : in std_logic_vector(0 downto 0);
GTYE4_COMMON_BGRCALOVRD : in std_logic_vector(4 downto 0);
GTYE4_COMMON_BGRCALOVRDENB : in std_logic_vector(0 downto 0);
GTYE4_COMMON_DRPADDR : in std_logic_vector(15 downto 0);
GTYE4_COMMON_DRPCLK : in std_logic_vector(0 downto 0);
GTYE4_COMMON_DRPDI : in std_logic_vector(15 downto 0);
GTYE4_COMMON_DRPEN : in std_logic_vector(0 downto 0);
GTYE4_COMMON_DRPWE : in std_logic_vector(0 downto 0);
GTYE4_COMMON_GTGREFCLK0 : in std_logic_vector(0 downto 0);
GTYE4_COMMON_GTGREFCLK1 : in std_logic_vector(0 downto 0);
GTYE4_COMMON_GTNORTHREFCLK00 : in std_logic_vector(0 downto 0);
GTYE4_COMMON_GTNORTHREFCLK01 : in std_logic_vector(0 downto 0);
GTYE4_COMMON_GTNORTHREFCLK10 : in std_logic_vector(0 downto 0);
GTYE4_COMMON_GTNORTHREFCLK11 : in std_logic_vector(0 downto 0);
GTYE4_COMMON_GTREFCLK00 : in std_logic_vector(0 downto 0);
GTYE4_COMMON_GTREFCLK01 : in std_logic_vector(0 downto 0);
GTYE4_COMMON_GTREFCLK10 : in std_logic_vector(0 downto 0);
GTYE4_COMMON_GTREFCLK11 : in std_logic_vector(0 downto 0);
GTYE4_COMMON_GTSOUTHREFCLK00 : in std_logic_vector(0 downto 0);
GTYE4_COMMON_GTSOUTHREFCLK01 : in std_logic_vector(0 downto 0);
GTYE4_COMMON_GTSOUTHREFCLK10 : in std_logic_vector(0 downto 0);
GTYE4_COMMON_GTSOUTHREFCLK11 : in std_logic_vector(0 downto 0);
GTYE4_COMMON_PCIERATEQPLL0 : in std_logic_vector(2 downto 0);
GTYE4_COMMON_PCIERATEQPLL1 : in std_logic_vector(2 downto 0);
GTYE4_COMMON_PMARSVD0 : in std_logic_vector(7 downto 0);
GTYE4_COMMON_PMARSVD1 : in std_logic_vector(7 downto 0);
GTYE4_COMMON_QPLL0CLKRSVD0 : in std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL0CLKRSVD1 : in std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL0FBDIV : in std_logic_vector(7 downto 0);
GTYE4_COMMON_QPLL0LOCKDETCLK : in std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL0LOCKEN : in std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL0PD : in std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL0REFCLKSEL : in std_logic_vector(2 downto 0);
GTYE4_COMMON_QPLL0RESET : in std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL1CLKRSVD0 : in std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL1CLKRSVD1 : in std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL1FBDIV : in std_logic_vector(7 downto 0);
GTYE4_COMMON_QPLL1LOCKDETCLK : in std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL1LOCKEN : in std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL1PD : in std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL1REFCLKSEL : in std_logic_vector(2 downto 0);
GTYE4_COMMON_QPLL1RESET : in std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLLRSVD1 : in std_logic_vector(7 downto 0);
GTYE4_COMMON_QPLLRSVD2 : in std_logic_vector(4 downto 0);
GTYE4_COMMON_QPLLRSVD3 : in std_logic_vector(4 downto 0);
GTYE4_COMMON_QPLLRSVD4 : in std_logic_vector(7 downto 0);
GTYE4_COMMON_RCALENB : in std_logic_vector(0 downto 0);
GTYE4_COMMON_SDM0DATA : in std_logic_vector(24 downto 0);
GTYE4_COMMON_SDM0RESET : in std_logic_vector(0 downto 0);
GTYE4_COMMON_SDM0TOGGLE : in std_logic_vector(0 downto 0);
GTYE4_COMMON_SDM0WIDTH : in std_logic_vector(1 downto 0);
GTYE4_COMMON_SDM1DATA : in std_logic_vector(24 downto 0);
GTYE4_COMMON_SDM1RESET : in std_logic_vector(0 downto 0);
GTYE4_COMMON_SDM1TOGGLE : in std_logic_vector(0 downto 0);
GTYE4_COMMON_SDM1WIDTH : in std_logic_vector(1 downto 0);
GTYE4_COMMON_UBCFGSTREAMEN : in std_logic_vector(0 downto 0);
GTYE4_COMMON_UBDO : in std_logic_vector(15 downto 0);
GTYE4_COMMON_UBDRDY : in std_logic_vector(0 downto 0);
GTYE4_COMMON_UBENABLE : in std_logic_vector(0 downto 0);
GTYE4_COMMON_UBGPI : in std_logic_vector(1 downto 0);
GTYE4_COMMON_UBINTR : in std_logic_vector(1 downto 0);
GTYE4_COMMON_UBIOLMBRST : in std_logic_vector(0 downto 0);
GTYE4_COMMON_UBMBRST : in std_logic_vector(0 downto 0);
GTYE4_COMMON_UBMDMCAPTURE : in std_logic_vector(0 downto 0);
GTYE4_COMMON_UBMDMDBGRST : in std_logic_vector(0 downto 0);
GTYE4_COMMON_UBMDMDBGUPDATE : in std_logic_vector(0 downto 0);
GTYE4_COMMON_UBMDMREGEN : in std_logic_vector(3 downto 0);
GTYE4_COMMON_UBMDMSHIFT : in std_logic_vector(0 downto 0);
GTYE4_COMMON_UBMDMSYSRST : in std_logic_vector(0 downto 0);
GTYE4_COMMON_UBMDMTCK : in std_logic_vector(0 downto 0);
GTYE4_COMMON_UBMDMTDI : in std_logic_vector(0 downto 0);
GTYE4_COMMON_DRPDO : out std_logic_vector(15 downto 0);
GTYE4_COMMON_DRPRDY : out std_logic_vector(0 downto 0);
GTYE4_COMMON_PMARSVDOUT0 : out std_logic_vector(7 downto 0);
GTYE4_COMMON_PMARSVDOUT1 : out std_logic_vector(7 downto 0);
GTYE4_COMMON_QPLL0FBCLKLOST : out std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL0LOCK : out std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL0OUTCLK : out std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL0OUTREFCLK : out std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL0REFCLKLOST : out std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL1FBCLKLOST : out std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL1LOCK : out std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL1OUTCLK : out std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL1OUTREFCLK : out std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLL1REFCLKLOST : out std_logic_vector(0 downto 0);
GTYE4_COMMON_QPLLDMONITOR0 : out std_logic_vector(7 downto 0);
GTYE4_COMMON_QPLLDMONITOR1 : out std_logic_vector(7 downto 0);
GTYE4_COMMON_REFCLKOUTMONITOR0 : out std_logic_vector(0 downto 0);
GTYE4_COMMON_REFCLKOUTMONITOR1 : out std_logic_vector(0 downto 0);
GTYE4_COMMON_RXRECCLK0SEL : out std_logic_vector(1 downto 0);
GTYE4_COMMON_RXRECCLK1SEL : out std_logic_vector(1 downto 0);
GTYE4_COMMON_SDM0FINALOUT : out std_logic_vector(3 downto 0);
GTYE4_COMMON_SDM0TESTDATA : out std_logic_vector(14 downto 0);
GTYE4_COMMON_SDM1FINALOUT : out std_logic_vector(3 downto 0);
GTYE4_COMMON_SDM1TESTDATA : out std_logic_vector(14 downto 0);
GTYE4_COMMON_UBDADDR : out std_logic_vector(15 downto 0);
GTYE4_COMMON_UBDEN : out std_logic_vector(0 downto 0);
GTYE4_COMMON_UBDI : out std_logic_vector(15 downto 0);
GTYE4_COMMON_UBDWE : out std_logic_vector(0 downto 0);
GTYE4_COMMON_UBMDMTDO : out std_logic_vector(0 downto 0);
GTYE4_COMMON_UBRSVDOUT : out std_logic_vector(0 downto 0);
GTYE4_COMMON_UBTXUART : out std_logic_vector(0 downto 0)
);
end component;
begin
-- INPUT BUFFER
IBUFDS_GTE4_inst : IBUFDS_GTE4
generic map (
REFCLK_EN_TX_PATH => '0',
REFCLK_HROW_CK_SEL => "00",
REFCLK_ICNTL_RX => "00"
)
port map (
O => gtrefclk,
ODIV2 => gtrefclk_out2,
CEB => '0',
I => gtrefclk_p,
IB => gtrefclk_n
);
BUFG_GT_inst : BUFG_GT
port map (
O => buff_gtrefclk,
CE => '1',
CEMASK => '1',
CLR => '0',
CLRMASK => '1',
DIV => "000",
I => gtrefclk_out2
);
-- TRANSCEIVER COMMON BLOCK
gtye_common_wrapper_inst: comlbp_gtwizard_gtye4_common_wrapper
port map(
GTYE4_COMMON_BGBYPASSB => "1",
GTYE4_COMMON_BGMONITORENB => "1",
GTYE4_COMMON_BGPDB => "1",
GTYE4_COMMON_BGRCALOVRD => "10000",
GTYE4_COMMON_BGRCALOVRDENB => "1",
GTYE4_COMMON_DRPADDR => "0000000000000000",
GTYE4_COMMON_DRPCLK => "0",
GTYE4_COMMON_DRPDI => "0000000000000000",
GTYE4_COMMON_DRPEN => "0",
GTYE4_COMMON_DRPWE => "0",
GTYE4_COMMON_GTGREFCLK0 => "0",
GTYE4_COMMON_GTGREFCLK1 => "0",
GTYE4_COMMON_GTNORTHREFCLK00 => "0",
GTYE4_COMMON_GTNORTHREFCLK01 => "0",
GTYE4_COMMON_GTNORTHREFCLK10 => "0",
GTYE4_COMMON_GTNORTHREFCLK11 => "0",
GTYE4_COMMON_GTREFCLK00(0) => gtrefclk,
GTYE4_COMMON_GTREFCLK01(0) => gtrefclk,
GTYE4_COMMON_GTREFCLK10 => "0",
GTYE4_COMMON_GTREFCLK11 => "0",
GTYE4_COMMON_GTSOUTHREFCLK00 => "0",
GTYE4_COMMON_GTSOUTHREFCLK01 => "0",
GTYE4_COMMON_GTSOUTHREFCLK10 => "0",
GTYE4_COMMON_GTSOUTHREFCLK11 => "0",
GTYE4_COMMON_PCIERATEQPLL0 => "000",
GTYE4_COMMON_PCIERATEQPLL1 => "000",
GTYE4_COMMON_PMARSVD0 => "00000000",
GTYE4_COMMON_PMARSVD1 => "00000000",
GTYE4_COMMON_QPLL0CLKRSVD0 => "0",
GTYE4_COMMON_QPLL0CLKRSVD1 => "0",
GTYE4_COMMON_QPLL0FBDIV => "00000000",
GTYE4_COMMON_QPLL0LOCKDETCLK(0)=> freerun_clk,
GTYE4_COMMON_QPLL0LOCKEN => "1",
GTYE4_COMMON_QPLL0PD => "0",
GTYE4_COMMON_QPLL0REFCLKSEL => "001",
GTYE4_COMMON_QPLL0RESET(0) => qpll0reset,
GTYE4_COMMON_QPLL1CLKRSVD0 => "0",
GTYE4_COMMON_QPLL1CLKRSVD1 => "0",
GTYE4_COMMON_QPLL1FBDIV => "00000000",
GTYE4_COMMON_QPLL1LOCKDETCLK(0)=> freerun_clk,
GTYE4_COMMON_QPLL1LOCKEN => "1",
GTYE4_COMMON_QPLL1PD => "0",
GTYE4_COMMON_QPLL1REFCLKSEL => "001",
GTYE4_COMMON_QPLL1RESET(0) => qpll1reset,
GTYE4_COMMON_QPLLRSVD1 => "00000000",
GTYE4_COMMON_QPLLRSVD2 => "00000",
GTYE4_COMMON_QPLLRSVD3 => "00000",
GTYE4_COMMON_QPLLRSVD4 => "00000000",
GTYE4_COMMON_RCALENB => "1",
GTYE4_COMMON_SDM0DATA => "0000000000000000000000000",
GTYE4_COMMON_SDM0RESET => "0",
GTYE4_COMMON_SDM0TOGGLE => "0",
GTYE4_COMMON_SDM0WIDTH => "00",
GTYE4_COMMON_SDM1DATA => "0001100110011001100110011",
GTYE4_COMMON_SDM1RESET => "0",
GTYE4_COMMON_SDM1TOGGLE => "0",
GTYE4_COMMON_SDM1WIDTH => "00",
GTYE4_COMMON_UBCFGSTREAMEN => "0",
GTYE4_COMMON_UBDO => "0000000000000000",
GTYE4_COMMON_UBDRDY => "0",
GTYE4_COMMON_UBENABLE => "0",
GTYE4_COMMON_UBGPI => "00",
GTYE4_COMMON_UBINTR => "00",
GTYE4_COMMON_UBIOLMBRST => "0",
GTYE4_COMMON_UBMBRST => "0",
GTYE4_COMMON_UBMDMCAPTURE => "0",
GTYE4_COMMON_UBMDMDBGRST => "0",
GTYE4_COMMON_UBMDMDBGUPDATE => "0",
GTYE4_COMMON_UBMDMREGEN => "0000",
GTYE4_COMMON_UBMDMSHIFT => "0",
GTYE4_COMMON_UBMDMSYSRST => "0",
GTYE4_COMMON_UBMDMTCK => "0",
GTYE4_COMMON_UBMDMTDI => "0",
GTYE4_COMMON_DRPDO => open,
GTYE4_COMMON_DRPRDY => open,
GTYE4_COMMON_PMARSVDOUT0 => open,
GTYE4_COMMON_PMARSVDOUT1 => open,
GTYE4_COMMON_QPLL0FBCLKLOST(0) => qpll0fblost,
GTYE4_COMMON_QPLL0LOCK(0) => qpll0lock,
GTYE4_COMMON_QPLL0OUTCLK(0) => qpll0outclk,
GTYE4_COMMON_QPLL0OUTREFCLK(0) => qpll0refclk,
GTYE4_COMMON_QPLL0REFCLKLOST(0)=> qpll0reflost,
GTYE4_COMMON_QPLL1FBCLKLOST(0) => qpll1fblost,
GTYE4_COMMON_QPLL1LOCK(0) => qpll1lock,
GTYE4_COMMON_QPLL1OUTCLK(0) => qpll1outclk,
GTYE4_COMMON_QPLL1OUTREFCLK(0) => qpll1refclk,
GTYE4_COMMON_QPLL1REFCLKLOST(0)=> qpll1reflost,
GTYE4_COMMON_QPLLDMONITOR0 => open,
GTYE4_COMMON_QPLLDMONITOR1 => open,
GTYE4_COMMON_REFCLKOUTMONITOR0 => open,
GTYE4_COMMON_REFCLKOUTMONITOR1 => open,
GTYE4_COMMON_RXRECCLK0SEL => open,
GTYE4_COMMON_RXRECCLK1SEL => open,
GTYE4_COMMON_SDM0FINALOUT => open,
GTYE4_COMMON_SDM0TESTDATA => open,
GTYE4_COMMON_SDM1FINALOUT => open,
GTYE4_COMMON_SDM1TESTDATA => open,
GTYE4_COMMON_UBDADDR => open,
GTYE4_COMMON_UBDEN => open,
GTYE4_COMMON_UBDI => open,
GTYE4_COMMON_UBDWE => open,
GTYE4_COMMON_UBMDMTDO => open,
GTYE4_COMMON_UBRSVDOUT => open,
GTYE4_COMMON_UBTXUART => open
);
end architecture struct;
src/app_fofbnode/hdl/pkg_app_fofb_cellnode.vhd
+ 6
− 6
View file @ 7b721f7d
...@@ -45,19 +45,19 @@ package pkg_app_config is ...@@ -45,19 +45,19 @@ package pkg_app_config is
-- Region 0 is BPM data -- Region 0 is BPM data
constant C_DAQ0_IS_CONTINUOUS : natural := 0; constant C_DAQ0_IS_CONTINUOUS : natural := 0;
constant C_DAQ0_MAX_SAMPLES : natural := 16384; -- does not change HDL constant C_DAQ0_MAX_SAMPLES : natural := 16#02000000#; -- Buffer size / 16 bytes
constant C_DAQ0_CHANNELS_IN_TAB : natural := 3; constant C_DAQ0_CHANNELS_IN_TAB : natural := 4;
constant C_DAQ0_TAB_COUNT : natural := 1; constant C_DAQ0_TAB_COUNT : natural := 1;
constant C_DAQ0_TAB_CONTENTS : t_natural_vector := (2, 1, 0); constant C_DAQ0_TAB_CONTENTS : t_natural_vector := (4, 2, 1, 0);
constant C_DAQ0_BUF0_OFFSET : natural := 16#00000000#; constant C_DAQ0_BUF0_OFFSET : natural := 16#00000000#;
constant C_DAQ0_BUF1_OFFSET : natural := 16#10000000#; constant C_DAQ0_BUF1_OFFSET : natural := 16#10000000#;
-- Region 1 is Correction data -- Region 1 is Correction data
constant C_DAQ1_IS_CONTINUOUS : natural := 0; constant C_DAQ1_IS_CONTINUOUS : natural := 0;
constant C_DAQ1_MAX_SAMPLES : natural := 16384; -- does not change HDL constant C_DAQ1_MAX_SAMPLES : natural := 16#04000000#; -- Buffer size / 8 bytes
constant C_DAQ1_CHANNELS_IN_TAB : natural := 1; constant C_DAQ1_CHANNELS_IN_TAB : natural := 2;
constant C_DAQ1_TAB_COUNT : natural := 1; constant C_DAQ1_TAB_COUNT : natural := 1;
constant C_DAQ1_TAB_CONTENTS : t_natural_vector := (0=>3); constant C_DAQ1_TAB_CONTENTS : t_natural_vector := (4, 3);
constant C_DAQ1_BUF0_OFFSET : natural := 16#20000000#; constant C_DAQ1_BUF0_OFFSET : natural := 16#20000000#;
constant C_DAQ1_BUF1_OFFSET : natural := 16#30000000#; constant C_DAQ1_BUF1_OFFSET : natural := 16#30000000#;
......
src/app_fofbnode/hdl/pkg_app_fofb_centralnode.vhd
+ 12
− 12
View file @ 7b721f7d
...@@ -72,23 +72,23 @@ package pkg_app_config is ...@@ -72,23 +72,23 @@ package pkg_app_config is
constant C_DAQ_BURST_LEN_ARRAY : t_natural_vector := (16,16,16); constant C_DAQ_BURST_LEN_ARRAY : t_natural_vector := (16,16,16);
constant C_DAQ_FIFO_DEPTH_ARRAY : t_natural_vector := (1024,1024,1024); constant C_DAQ_FIFO_DEPTH_ARRAY : t_natural_vector := (1024,1024,1024);
-- Region 0 is BPM data -- Region 0 is continuous data
constant C_DAQ0_IS_CONTINUOUS : natural := 1; constant C_DAQ0_IS_CONTINUOUS : natural := 1;
constant C_DAQ0_MAX_SAMPLES : natural := 16#00800000#; -- Buffer size / 16 bytes constant C_DAQ0_MAX_SAMPLES : natural := 16#04000000#; -- Buffer size / 8 bytes
constant C_DAQ0_CHANNELS_IN_TAB : natural := 3; constant C_DAQ0_CHANNELS_IN_TAB : natural := 2;
constant C_DAQ0_TAB_COUNT : natural := 1; constant C_DAQ0_TAB_COUNT : natural := 1;
constant C_DAQ0_TAB_CONTENTS : t_natural_vector := (2, 1, 0); constant C_DAQ0_TAB_CONTENTS : t_natural_vector := (1, 0);
constant C_DAQ0_BUF0_OFFSET : natural := 16#00000000#; constant C_DAQ0_BUF0_OFFSET : natural := 16#00000000#;
constant C_DAQ0_BUF1_OFFSET : natural := 16#08000000#; constant C_DAQ0_BUF1_OFFSET : natural := 16#10000000#;
-- Region 1 is Correction data -- Region 1 is pulsed data
constant C_DAQ1_IS_CONTINUOUS : natural := 1; constant C_DAQ1_IS_CONTINUOUS : natural := 0;
constant C_DAQ1_MAX_SAMPLES : natural := 16#02000000#; -- Buffer size / 4 bytes constant C_DAQ1_MAX_SAMPLES : natural := 16#04000000#; -- Buffer size / 8 bytes
constant C_DAQ1_CHANNELS_IN_TAB : natural := 1; constant C_DAQ1_CHANNELS_IN_TAB : natural := 2;
constant C_DAQ1_TAB_COUNT : natural := 1; constant C_DAQ1_TAB_COUNT : natural := 1;
constant C_DAQ1_TAB_CONTENTS : t_natural_vector := (0=>3); constant C_DAQ1_TAB_CONTENTS : t_natural_vector := (1, 0);
constant C_DAQ1_BUF0_OFFSET : natural := 16#10000000#; constant C_DAQ1_BUF0_OFFSET : natural := 16#20000000#;
constant C_DAQ1_BUF1_OFFSET : natural := 16#18000000#; constant C_DAQ1_BUF1_OFFSET : natural := 16#20000000#; -- Won't be used
-- not used, only two regions -- not used, only two regions
constant C_DAQ2_IS_CONTINUOUS : natural := 0; constant C_DAQ2_IS_CONTINUOUS : natural := 0;
......
src/app_fofbnode/hdl/top_app_cellnode.vhd
+ 395
− 64
View file @ 7b721f7d
This diff is collapsed.
src/app_fofbnode/hdl/top_app_centralnode.vhd
+ 109
− 26
View file @ 7b721f7d
...@@ -168,6 +168,20 @@ architecture struct of bsp_fmc2zup_payload is ...@@ -168,6 +168,20 @@ architecture struct of bsp_fmc2zup_payload is
signal r_daq_trigger : std_logic_vector(1 downto 0); signal r_daq_trigger : std_logic_vector(1 downto 0);
signal daq_data : t_32b_slv_vector(3 downto 0); signal daq_data : t_32b_slv_vector(3 downto 0);
signal daq_irq : std_logic_vector(C_DAQ_REGIONS-1 downto 0); signal daq_irq : std_logic_vector(C_DAQ_REGIONS-1 downto 0);
signal r_last_seq : std_logic_vector(7 downto 0);
signal axis_daqs00_tdata : std_logic_vector(63 downto 0);
signal axis_daqs00_tvalid : std_logic;
signal axis_daqs01_tdata : std_logic_vector(63 downto 0);
signal axis_daqs01_tvalid : std_logic;
signal axis_daqs02_tdata : std_logic_vector(63 downto 0);
signal axis_daqs02_tvalid : std_logic;
signal axis_daqs03_tdata : std_logic_vector(63 downto 0);
signal axis_daqs03_tvalid : std_logic;
signal axis_daqm00_tdata : std_logic_vector(63 downto 0);
signal axis_daqm00_tvalid : std_logic;
signal axis_daqm00_tready : std_logic;
-- Other signals -- Other signals
signal rst : std_logic; signal rst : std_logic;
...@@ -645,6 +659,97 @@ begin ...@@ -645,6 +659,97 @@ begin
-- ============================================================================= -- -- ============================================================================= --
-- == DAQ SYSTEM == -- -- == DAQ SYSTEM == --
-- ============================================================================= -- -- ============================================================================= --
-- Temporary source: trigger on new bpm seq
p_trig_seq:process(axis_clk, axis_rstn)
begin
if axis_rstn = '0' then
r_last_seq <= (others => '0');
axis_daqs00_tvalid <= '0';
elsif rising_edge(axis_clk) then
if (axis_pkt_rx_tvalid and axis_pkt_rx_tready) = '1' then
r_last_seq <= axis_pkt_rx_tuser(7 downto 0);
if r_last_seq /= axis_pkt_rx_tuser(7 downto 0) then
axis_daqs00_tvalid <= '1';
else
axis_daqs00_tvalid <= '0';
end if;
else
axis_daqs00_tvalid <= '0';
end if;
end if;
end process;
axis_daqs00_tdata(63 downto 48) <= x"8005"; -- Trigger source, new bpm seq event
axis_daqs00_tdata(47 downto 32) <= x"00"&axis_pkt_rx_tuser(7 downto 0); -- Ancillary is seq num
axis_daqs00_tdata(31 downto 0) <= timeref(31 downto 0); -- Timestamp
axis_daqs01_tdata(63 downto 56) <= x"40"; -- BPM x source
axis_daqs01_tdata(55 downto 48) <= axis_pkt_rx_tdata(71 downto 64); -- BPM id
axis_daqs01_tdata(47 downto 32) <= x"00"&axis_pkt_rx_tuser(7 downto 0); -- Ancillary is seq num
axis_daqs01_tdata(31 downto 0) <= axis_pkt_rx_tdata(31 downto 0); -- Position
axis_daqs01_tvalid <= axis_pkt_rx_tvalid and axis_pkt_rx_tready;
axis_daqs02_tdata(63 downto 56) <= x"42"; -- BPM y source
axis_daqs02_tdata(55 downto 48) <= axis_pkt_rx_tdata(71 downto 64); -- BPM id
axis_daqs02_tdata(47 downto 32) <= x"00"&axis_pkt_rx_tuser(7 downto 0); -- Ancillary is seq num
axis_daqs02_tdata(31 downto 0) <= axis_pkt_rx_tdata(63 downto 32); -- Position
axis_daqs02_tvalid <= axis_pkt_rx_tvalid and axis_pkt_rx_tready;
axis_daqs03_tdata(63 downto 56) <= x"B0"; -- PSC source
axis_daqs03_tdata(55 downto 48) <= axis_pscgen_tdata_pscid; -- PSC id
axis_daqs03_tdata(47 downto 32) <= x"00"&axis_pscgen_tuser; -- Ancillary is seq num
axis_daqs03_tdata(31 downto 16) <= (others => axis_pscgen_tdata_value(15)); -- Sign extension
axis_daqs03_tdata(15 downto 0) <= axis_pscgen_tdata_value; -- Value
axis_daqs03_tvalid <= axis_pscgen_tvalid;
-- DAQ interconnect data source
inst_daq_axis_ic: entity work.axis_ic_capt
port map (
aclk => axis_clk,
s00_axis_aclk => axis_clk,
s01_axis_aclk => axis_clk,
s02_axis_aclk => axis_clk,
s03_axis_aclk => axis_clk,
m00_axis_aclk => axis_clk,
aresetn => axis_rstn,
s00_axis_aresetn => axis_rstn,
s01_axis_aresetn => axis_rstn,
s02_axis_aresetn => axis_rstn,
s03_axis_aresetn => axis_rstn,
m00_axis_aresetn => axis_rstn,
s00_axis_tvalid => axis_daqs00_tvalid,
s00_axis_tready => open, --no back pressure
s00_axis_tdata => axis_daqs00_tdata,
s01_axis_tvalid => axis_daqs01_tvalid,
s01_axis_tready => open, --no back pressure
s01_axis_tdata => axis_daqs01_tdata,
s02_axis_tvalid => axis_daqs02_tvalid,
s02_axis_tready => open, --no back pressure
s02_axis_tdata => axis_daqs02_tdata,
s03_axis_tvalid => axis_daqs03_tvalid,
s03_axis_tready => open, --no back pressure
s03_axis_tdata => axis_daqs03_tdata,
m00_axis_tvalid => axis_daqm00_tvalid,
m00_axis_tready => axis_daqm00_tready,
m00_axis_tdata => axis_daqm00_tdata,
s00_arb_req_suppress => C_LOGIC_ZERO,
s01_arb_req_suppress => C_LOGIC_ZERO,
s02_arb_req_suppress => C_LOGIC_ZERO,
s03_arb_req_suppress => C_LOGIC_ZERO
);
axis_daqm00_tready <= '1'; -- no back pressure from DAQ
inst_daq: entity work.daq_top inst_daq: entity work.daq_top
generic map ( generic map (
g_fifo_arch => "ULTRASCALE", g_fifo_arch => "ULTRASCALE",
...@@ -679,32 +784,10 @@ begin ...@@ -679,32 +784,10 @@ begin
m_axi4_daq_s2m <= f_common_to_bsp(pi_payload.s_axi4_daq); m_axi4_daq_s2m <= f_common_to_bsp(pi_payload.s_axi4_daq);
po_payload.s_axi4_daq <= f_common_to_bsp(m_axi4_daq_m2s); po_payload.s_axi4_daq <= f_common_to_bsp(m_axi4_daq_m2s);
------------------------------------------------------- daq_data(0) <= axis_daqm00_tdata(31 downto 0);
-- Mapping data channel daq_data(1) <= axis_daqm00_tdata(63 downto 32);
-- Region 0
-- 2*4 bytes for a xy position data
-- 1 byte for bpmid
-- 1 byte for seq
-- Region 1
-- 2 bytes for a correction data
-- 1 byte for pscid
-- 1 byte for seq
--
daq_data(0) <= axis_pkt_rx_tdata(31 downto 0);
--
daq_data(1) <= axis_pkt_rx_tdata(63 downto 32);
--
daq_data(2)(7 downto 0) <= axis_pkt_rx_tdata(71 downto 64);
daq_data(2)(15 downto 8) <= (others => '0');
daq_data(2)(23 downto 16) <= axis_pkt_rx_tuser;
daq_data(2)(31 downto 24) <= (others => '0');
--
daq_data(3)(15 downto 0) <= axis_pscgen_tdata_value;
daq_data(3)(23 downto 16) <= axis_pscgen_tdata_pscid;
daq_data(3)(31 downto 24) <= axis_pscgen_tuser;
daq_strobe(0) <= axis_pkt_rx_tvalid and axis_pkt_rx_tready; daq_strobe(0) <= axis_daqm00_tvalid;
daq_strobe(1) <= axis_pscgen_tvalid;
daq_stop <= addrmap_o.daq_control.stop.data(0); daq_stop <= addrmap_o.daq_control.stop.data(0);
......
src/app_fofbnode/rdl/app_fofb_cellnode.rdl
+ 4
− 0
View file @ 7b721f7d
...@@ -87,6 +87,10 @@ addrmap app_fofb_cellnode { ...@@ -87,6 +87,10 @@ addrmap app_fofb_cellnode {
ccn_packeter ccn_packeter_0; ccn_packeter ccn_packeter_0;
ccn_unpacketer ccn_unpacketer_0; ccn_unpacketer ccn_unpacketer_0;
combpm combpm_0; combpm combpm_0;
comlbp comlbp_0;
comlbp comlbp_1;
comlbp comlbp_2;
comlbp comlbp_3;
comcorr comcorr_0; comcorr comcorr_0;
pscgen pscgen_0; pscgen pscgen_0;
daq daq_0; daq daq_0;
......
src/app_fofbnode/tcl/gen_ip_cellnode.tcl
+ 48
− 9
View file @ 7b721f7d
...@@ -3,25 +3,64 @@ ...@@ -3,25 +3,64 @@
set ProjectDirPath [file join ${::fwfwk::PrjBuildPath} ${::fwfwk::PrjBuildName}] set ProjectDirPath [file join ${::fwfwk::PrjBuildPath} ${::fwfwk::PrjBuildName}]
## ------------------------------------- ## ## ------------------------------------- ##
## UPSTREAM FIFO ## UPSTREAM INTERCONNECT
## ------------------------------------- ## ## ------------------------------------- ##
set ipName "axis_upstream_fifo" set ipName "axis_com51_rx"
# 5 to 1 axis interconnect for bpm/lpb reception
set xcipath [create_ip \ set xcipath [create_ip \
-name axis_data_fifo \ -name axis_interconnect \
-vendor xilinx.com \ -vendor xilinx.com \
-library ip -version 2.0 \ -library ip -version 1.1 \
-module_name $ipName] -module_name $ipName]
set_property -dict [list \ set_property -dict [list \
CONFIG.TDATA_NUM_BYTES {10} \ CONFIG.C_NUM_SI_SLOTS {5} \
CONFIG.TUSER_WIDTH {8} \ CONFIG.SWITCH_TDATA_NUM_BYTES {12} \
CONFIG.FIFO_DEPTH {64} \ CONFIG.HAS_TSTRB {false} \
CONFIG.IS_ACLK_ASYNC {1} \ CONFIG.HAS_TKEEP {false} \
CONFIG.HAS_AFULL {1} \ CONFIG.HAS_TLAST {false} \
CONFIG.HAS_TID {false} \
CONFIG.HAS_TDEST {false} \
CONFIG.HAS_TUSER {false} \
CONFIG.SWITCH_TUSER_BITS_PER_BYTE {1} \
CONFIG.ARBITER_TYPE {Fixed} \
CONFIG.C_S00_AXIS_IS_ACLK_ASYNC {0} \
CONFIG.C_S01_AXIS_IS_ACLK_ASYNC {1} \
CONFIG.C_S02_AXIS_IS_ACLK_ASYNC {1} \
CONFIG.C_S03_AXIS_IS_ACLK_ASYNC {1} \
CONFIG.C_S04_AXIS_IS_ACLK_ASYNC {1} \
CONFIG.M00_AXIS_FIFO_MODE {1_(Normal)} \
CONFIG.C_M00_AXIS_FIFO_DEPTH {128} \
CONFIG.S00_AXIS_FIFO_MODE {1_(Normal)} \
CONFIG.C_S00_AXIS_FIFO_DEPTH {128} \
CONFIG.S01_AXIS_FIFO_MODE {1_(Normal)} \
CONFIG.C_S01_AXIS_FIFO_DEPTH {128} \
CONFIG.S02_AXIS_FIFO_MODE {1_(Normal)} \
CONFIG.C_S02_AXIS_FIFO_DEPTH {128} \
CONFIG.S03_AXIS_FIFO_MODE {1_(Normal)} \
CONFIG.C_S03_AXIS_FIFO_DEPTH {128} \
CONFIG.S04_AXIS_FIFO_MODE {1_(Normal)} \
CONFIG.C_S04_AXIS_FIFO_DEPTH {128} \
CONFIG.SWITCH_PACKET_MODE {false} \
CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {1} \
CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} \
CONFIG.M00_AXIS_TDATA_NUM_BYTES {12} \
CONFIG.S00_AXIS_TDATA_NUM_BYTES {12} \
CONFIG.S01_AXIS_TDATA_NUM_BYTES {12} \
CONFIG.S02_AXIS_TDATA_NUM_BYTES {12} \
CONFIG.S03_AXIS_TDATA_NUM_BYTES {12} \
CONFIG.S04_AXIS_TDATA_NUM_BYTES {12} \
CONFIG.M00_S00_CONNECTIVITY {true} \
CONFIG.M00_S01_CONNECTIVITY {true} \
CONFIG.M00_S02_CONNECTIVITY {true} \
CONFIG.M00_S03_CONNECTIVITY {true} \
CONFIG.M00_S04_CONNECTIVITY {true} \
] [get_ips $ipName] ] [get_ips $ipName]
generate_target all [get_files ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci] generate_target all [get_files ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci]
export_ip_user_files -of_objects [get_files ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci] -no_script -sync -force -quiet export_ip_user_files -of_objects [get_files ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci] create_ip_run [get_files -of_objects [get_fileset sources_1] ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci]
src/app_fofbnode/tcl/gen_ip_centralnode.tcl
+ 48
− 0
View file @ 7b721f7d
...@@ -107,3 +107,51 @@ generate_target all [get_files ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipN ...@@ -107,3 +107,51 @@ generate_target all [get_files ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipN
export_ip_user_files -of_objects [get_files ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci] -no_script -sync -force -quiet export_ip_user_files -of_objects [get_files ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci] create_ip_run [get_files -of_objects [get_fileset sources_1] ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci]
## ------------------------------------- ##
## CAPTURE INTERCONNECT
## ------------------------------------- ##
set ipName "axis_ic_capt"
set xcipath [create_ip \
-name axis_interconnect \
-vendor xilinx.com \
-library ip -version 1.1 \
-module_name $ipName]
set_property -dict [list \
CONFIG.C_NUM_SI_SLOTS {4} \
CONFIG.SWITCH_TDATA_NUM_BYTES {8} \
CONFIG.HAS_TSTRB {false} \
CONFIG.HAS_TKEEP {false} \
CONFIG.HAS_TLAST {false} \
CONFIG.HAS_TID {false} \
CONFIG.HAS_TDEST {false} \
CONFIG.HAS_TUSER {false} \
CONFIG.ARBITER_TYPE {Fixed} \
CONFIG.S00_AXIS_FIFO_MODE {1_(Normal)} \
CONFIG.C_S00_AXIS_FIFO_DEPTH {128} \
CONFIG.S01_AXIS_FIFO_MODE {1_(Normal)} \
CONFIG.C_S01_AXIS_FIFO_DEPTH {128} \
CONFIG.S02_AXIS_FIFO_MODE {1_(Normal)} \
CONFIG.C_S02_AXIS_FIFO_DEPTH {128} \
CONFIG.S03_AXIS_FIFO_MODE {1_(Normal)} \
CONFIG.C_S03_AXIS_FIFO_DEPTH {128} \
CONFIG.SWITCH_PACKET_MODE {false} \
CONFIG.C_SWITCH_MAX_XFERS_PER_ARB {1} \
CONFIG.C_SWITCH_NUM_CYCLES_TIMEOUT {0} \
CONFIG.M00_AXIS_TDATA_NUM_BYTES {8} \
CONFIG.S00_AXIS_TDATA_NUM_BYTES {8} \
CONFIG.S01_AXIS_TDATA_NUM_BYTES {8} \
CONFIG.S02_AXIS_TDATA_NUM_BYTES {8} \
CONFIG.S03_AXIS_TDATA_NUM_BYTES {8} \
CONFIG.M00_S01_CONNECTIVITY {true} \
CONFIG.M00_S02_CONNECTIVITY {true} \
CONFIG.M00_S03_CONNECTIVITY {true} \
] [get_ips $ipName]
generate_target all [get_files ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci]
export_ip_user_files -of_objects [get_files ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci] -no_script -sync -force -quiet
create_ip_run [get_files -of_objects [get_fileset sources_1] ${ProjectDirPath}.srcs/sources_1/ip/$ipName/$ipName.xci]
src/app_fofbnode/tcl/main.tcl
+ 7
− 2
View file @ 7b721f7d
...@@ -15,6 +15,7 @@ proc init {} { ...@@ -15,6 +15,7 @@ proc init {} {
# Modules for CellNodes # Modules for CellNodes
if {$::fwfwk::ProjectConf == "CellNode"} { if {$::fwfwk::ProjectConf == "CellNode"} {
addSrcModule combpm $::fwfwk::SrcPath/combpm/tcl/main.tcl addSrcModule combpm $::fwfwk::SrcPath/combpm/tcl/main.tcl
addSrcModule comlbp $::fwfwk::SrcPath/comlbp/tcl/main.tcl
addSrcModule comcorr $::fwfwk::SrcPath/comcorr/tcl/main.tcl addSrcModule comcorr $::fwfwk::SrcPath/comcorr/tcl/main.tcl
} }
...@@ -34,6 +35,7 @@ proc init {} { ...@@ -34,6 +35,7 @@ proc init {} {
if {$::fwfwk::ProjectConf == "CellNode"} { if {$::fwfwk::ProjectConf == "CellNode"} {
set ccn_packet::CCN_DPKT_W 80 set ccn_packet::CCN_DPKT_W 80
set ccn_packet::CCN_UPKT_W 48 set ccn_packet::CCN_UPKT_W 48
set comlbp::Config(GT_LOC) [list X0Y4 X0Y5 X0Y6 X0Y7]
set ccn_ethernet::Config(GTH_LOC) [list X0Y5] set ccn_ethernet::Config(GTH_LOC) [list X0Y5]
} }
if {$::fwfwk::ProjectConf == "CentralNode"} { if {$::fwfwk::ProjectConf == "CentralNode"} {
...@@ -57,10 +59,13 @@ proc setSources {} { ...@@ -57,10 +59,13 @@ proc setSources {} {
# ---------------------------------- # ----------------------------------
# Configuration related sources # Configuration related sources
if {$::fwfwk::ProjectConf == "CellNode"} { if {$::fwfwk::ProjectConf == "CellNode"} {
lappend Vhdl ../hdl/top_app_cellnode.vhd lappend Vhdl {"../hdl/top_app_cellnode.vhd" "VHDL 2008"}
lappend Vhdl ../hdl/pkg_app_fofb_cellnode.vhd lappend Vhdl ../hdl/pkg_app_fofb_cellnode.vhd
lappend Vhdl ../hdl/rtm_cactus_top.vhd lappend Vhdl ../hdl/rtm_cactus_top.vhd
lappend Vhdl ../hdl/gtye_common.vhd
lappend Verilog ../hdl/comlbp_gtwizard_gtye4_common_wrapper.v
lappend Xdc ../con/physical_c2c.xdc lappend Xdc ../con/physical_c2c.xdc
lappend Xdc ../con/physical_fmc1.xdc
} }
if {$::fwfwk::ProjectConf == "CentralNode"} { if {$::fwfwk::ProjectConf == "CentralNode"} {
...@@ -72,7 +77,6 @@ proc setSources {} { ...@@ -72,7 +77,6 @@ proc setSources {} {
# Sources for QPLL common # Sources for QPLL common
lappend Vhdl ../hdl/gthe_common.vhd lappend Vhdl ../hdl/gthe_common.vhd
lappend Verilog ../hdl/combpm_gtwizard_gthe4_common_wrapper.v lappend Verilog ../hdl/combpm_gtwizard_gthe4_common_wrapper.v
lappend Verilog ../hdl/gtwizard_ultrascale_v1_7_gthe4_common.v
lappend Xdc ../con/physical_fmc2.xdc lappend Xdc ../con/physical_fmc2.xdc
} }
...@@ -99,6 +103,7 @@ proc setAddressSpace {} { ...@@ -99,6 +103,7 @@ proc setAddressSpace {} {
if {$::fwfwk::ProjectConf == "CellNode"} { if {$::fwfwk::ProjectConf == "CellNode"} {
addAddressSpace AddressSpace "combpm_0" INST {} combpm::AddressSpace addAddressSpace AddressSpace "combpm_0" INST {} combpm::AddressSpace
addAddressSpace AddressSpace "comlbp_0" INST {} comlbp::AddressSpace
addAddressSpace AddressSpace "comcorr_0" INST {} comcorr::AddressSpace addAddressSpace AddressSpace "comcorr_0" INST {} comcorr::AddressSpace
} }
......
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment

The place to be for your source code