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fofbnode_fpga
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DG
FOFB
fofbnode_fpga
Commits
2956807a
Commit
2956807a
authored
May 17, 2024
by
BRONES Romain
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Add fifo for combpm before interconnect
parent
251be847
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src/app_fofbnode/hdl/top_app_cellnode.vhd
+53
-4
53 additions, 4 deletions
src/app_fofbnode/hdl/top_app_cellnode.vhd
with
53 additions
and
4 deletions
src/app_fofbnode/hdl/top_app_cellnode.vhd
+
53
−
4
View file @
2956807a
...
@@ -114,6 +114,9 @@ architecture struct of bsp_fmc2zup_payload is
...
@@ -114,6 +114,9 @@ architecture struct of bsp_fmc2zup_payload is
signal
clk_combpm
:
std_logic
;
signal
clk_combpm
:
std_logic
;
signal
axis_combpm_tdata
:
std_logic_vector
(
127
downto
0
);
signal
axis_combpm_tdata
:
std_logic_vector
(
127
downto
0
);
signal
axis_combpm_tvalid
:
std_logic
;
signal
axis_combpm_tvalid
:
std_logic
;
signal
axis_combpm_sync_tvalid
:
std_logic
;
signal
axis_combpm_sync_tready
:
std_logic
;
signal
axis_combpm_sync_tdata
:
std_logic_vector
(
95
downto
0
);
-- COMLBP signals
-- COMLBP signals
signal
comlbp_am2s
:
t_a_comlbp_m2s
;
signal
comlbp_am2s
:
t_a_comlbp_m2s
;
...
@@ -419,6 +422,52 @@ begin
...
@@ -419,6 +422,52 @@ begin
s_axi_s2m
=>
addrmap_i
.
combpm_0
s_axi_s2m
=>
addrmap_i
.
combpm_0
);
);
inst_upstream_lbp_fifo
:
xpm_fifo_axis
generic
map
(
CLOCKING_MODE
=>
"independent_clock"
,
FIFO_DEPTH
=>
64
,
RD_DATA_COUNT_WIDTH
=>
7
,
WR_DATA_COUNT_WIDTH
=>
7
,
RELATED_CLOCKS
=>
0
,
TDATA_WIDTH
=>
96
)
port
map
(
s_aresetn
=>
pi_payload
.
m_axi4l_reg_areset_n
,
almost_empty_axis
=>
open
,
almost_full_axis
=>
open
,
dbiterr_axis
=>
open
,
sbiterr_axis
=>
open
,
prog_empty_axis
=>
open
,
prog_full_axis
=>
open
,
rd_data_count_axis
=>
open
,
wr_data_count_axis
=>
open
,
injectdbiterr_axis
=>
'0'
,
injectsbiterr_axis
=>
'0'
,
s_aclk
=>
clk_combpm
,
s_axis_tvalid
=>
axis_combpm_tvalid
,
s_axis_tdata
=>
x"00"
&
axis_combpm_tdata
(
127
downto
120
)
&
axis_combpm_tdata
(
79
downto
0
),
s_axis_tready
=>
open
,
s_axis_tdest
=>
(
others
=>
'0'
),
s_axis_tid
=>
(
others
=>
'0'
),
s_axis_tkeep
=>
(
others
=>
'0'
),
s_axis_tlast
=>
'0'
,
s_axis_tstrb
=>
(
others
=>
'0'
),
s_axis_tuser
=>
(
others
=>
'0'
),
m_aclk
=>
pi_payload
.
m_axi4l_reg_aclk
,
m_axis_tdata
=>
axis_combpm_sync_tdata
,
m_axis_tready
=>
axis_combpm_sync_tready
,
m_axis_tvalid
=>
axis_combpm_sync_tvalid
--m_axis_tdest => open,
--m_axis_tid => open,
--m_axis_tkeep => open,
--m_axis_tlast => open,
--m_axis_tstrb => open,
--m_axis_tuser => open
);
------------
------------
-- COMLBP --
-- COMLBP --
------------
------------
...
@@ -548,7 +597,7 @@ begin
...
@@ -548,7 +597,7 @@ begin
inst_rx_axis_ic
:
entity
work
.
axis_com51_rx
inst_rx_axis_ic
:
entity
work
.
axis_com51_rx
port
map
(
port
map
(
aclk
=>
pi_payload
.
m_axi4l_reg_aclk
,
aclk
=>
pi_payload
.
m_axi4l_reg_aclk
,
s00_axis_aclk
=>
clk_combpm
,
s00_axis_aclk
=>
pi_payload
.
m_axi4l_reg_aclk
,
s01_axis_aclk
=>
pi_payload
.
m_axi4l_reg_aclk
,
s01_axis_aclk
=>
pi_payload
.
m_axi4l_reg_aclk
,
s02_axis_aclk
=>
pi_payload
.
m_axi4l_reg_aclk
,
s02_axis_aclk
=>
pi_payload
.
m_axi4l_reg_aclk
,
s03_axis_aclk
=>
pi_payload
.
m_axi4l_reg_aclk
,
s03_axis_aclk
=>
pi_payload
.
m_axi4l_reg_aclk
,
...
@@ -563,9 +612,9 @@ begin
...
@@ -563,9 +612,9 @@ begin
s04_axis_aresetn
=>
pi_payload
.
m_axi4l_reg_areset_n
,
s04_axis_aresetn
=>
pi_payload
.
m_axi4l_reg_areset_n
,
m00_axis_aresetn
=>
pi_payload
.
m_axi4l_reg_areset_n
,
m00_axis_aresetn
=>
pi_payload
.
m_axi4l_reg_areset_n
,
s00_axis_tvalid
=>
axis_combpm_tvalid
,
s00_axis_tvalid
=>
axis_combpm_
sync_
tvalid
,
s00_axis_tready
=>
open
,
s00_axis_tready
=>
axis_combpm_sync_tready
,
s00_axis_tdata
=>
x"00"
&
axis_combpm_tdata
(
127
downto
120
)
&
axis_combpm_tdata
(
79
downto
0
)
,
s00_axis_tdata
=>
axis_combpm_
sync_
tdata
,
s01_axis_tvalid
=>
axis_comlbp_sync_tvalid
(
0
),
s01_axis_tvalid
=>
axis_comlbp_sync_tvalid
(
0
),
s01_axis_tready
=>
axis_comlbp_sync_tready
(
0
),
s01_axis_tready
=>
axis_comlbp_sync_tready
(
0
),
...
...
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