pscgen.rdl

`include "pscgen.vh" //automatically created and added by fwk with conf variables such a C_VERSION ...

/* default values of defined variables */
`ifndef C_ID
`define C_ID 0x507E1712
`endif
`ifndef C_VERSION
`define C_VERSION 0x00000000
`endif

addrmap pscgen {
  name = "Signal generator for power supplies controller.";
  desyrdl_interface = "AXI4L";

  reg {
    desc="Module Identification Number";
    default sw = r;
    default hw = r;
    field {} data[32] = `C_ID;
  } ID @0x00;

  reg {
    desc="Module Version Number";
    default sw = r;
    default hw = r;
    field {} data [32];
  } VERSION @0x04;

  reg {
    desc = "Control register";
    default sw = rw;
    default hw = r;
    field {} enable;
  } CONTROL ;

  reg {
    desc = "Ticker rate register";
    default sw = rw;
    default hw = r;
    field {} data[32];
  } TICKER_RATE ;

  reg {
    desc = "Table scan depth register";
    default sw = rw;
    default hw = r;
    field {} data[`C_W_TIDX];
  } TABLE_DEPTH ;

  external mem {
    desc = "Phase increment table";
    memwidth = `C_W_PHASE;
    mementries = 2**`C_W_TIDX;
  } TABLE_PHASE_INCR;


  external mem {
    desc = "Phase offset and reset table";
    memwidth = `C_W_PHASE+1;
    mementries = 2**`C_W_TIDX;
  } TABLE_PHASE_OFFS;

  external mem {
    desc = "Signal scale and offset table";
    memwidth = `C_W_SCALE+`C_W_OFFSET;
    mementries = 2**`C_W_TIDX;
  } TABLE_SCALE;

};