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Commit ca8c38a2 authored by Jean-Paul RICAUD's avatar Jean-Paul RICAUD
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Corrected board definition files 

 On branch development

	modified:   board/Macbeth/1.0/board.xml
	modified:   board/Macbeth/1.0/part0_pins.xml
	modified:   board/Macbeth/1.0/preset.xml
	modified:   board/Macbeth/1.0/xitem.json
parent e159d0c2
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FPGA/board/Macbeth/1.0/board.xml
+ 536
− 539
View file @ ca8c38a2
......@@ -11,7 +11,7 @@
License for the specific language governing permissions and limitations
under the License. -->
<board schema_version="2.2" vendor="Synchrotron SOLEIL" name="Macbeth k26c" display_name="Macbeth Kria K26C SOM" url="https://gitlab.com/ohwr/project/macbeth" preset_file="preset.xml" supports_ced="true">
<board schema_version="2.2" vendor="Synchrotron-SOLEIL" name="Macbeth k26c" display_name="Macbeth Kria K26C SOM" url="https://gitlab.com/ohwr/project/macbeth" preset_file="preset.xml" supports_ced="true">
<images>
<image name="macbeth.png" display_name="Macbeth Kria K26C SOM" sub_type="board">
......@@ -37,7 +37,7 @@
<components>
<component name="som240_1_connector" type="connector" sub_type="som" display_name="Connector 1 on K26 SOM (SOM240_1)">
<component name="som240_1_connector" type="connector" sub_type="som" display_name="Connector 1 on K26 SOM (SOM240_1)" major_group="SOM240_1">
<pins>
<pin index="1" name="som240_1_a1" ></pin>
<pin index="2" name="som240_1_a2" ></pin>
......@@ -285,7 +285,7 @@
</pins>
</component>
<component name="som240_2_connector" type="connector" sub_type="som" display_name="Connector 2 on K26 SOM (SOM240_2)">
<component name="som240_2_connector" type="connector" sub_type="som" display_name="Connector 2 on K26 SOM (SOM240_2)" major_group="SOM240_2">
<pins>
<pin index="1" name="som240_2_a1" ></pin>
<pin index="2" name="som240_2_a2" ></pin>
......@@ -535,7 +535,6 @@
<component name="part0" display_name="VISION SOM Evaluation Platform" type="fpga" part_name="xck26-sfvc784-2LV-c" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.xilinx.com">
<description>FPGA part on the board</description>
<interfaces>
<interface mode="master" name="ps8_fixedio" type="xilinx.com:zynq_ultra_ps_e:fixedio_rtl:1.0" of_component="ps8_fixedio" preset_proc="mpsoc_preset_vsom">
<preferred_ips>
......@@ -543,12 +542,10 @@
</preferred_ips>
</interface>
</interfaces>
</component>
<component name="ps8_fixedio" display_name="MPSoC fixedio Interface on Vision SOM" type="chip" sub_type="fixed_io" major_group=""/>
</components>
<jtag_chains>
......
FPGA/board/Macbeth/1.0/part0_pins.xml
+ 1
− 1
View file @ ca8c38a2
......@@ -208,7 +208,7 @@
<pin index="186" name ="som240_2_d28" iostandard="LVCMOS18" loc="AF6" pcb_min_delay="0.31895" pcb_max_delay="0.38983"/>
<pin index="187" name ="som240_2_d30" iostandard="LVCMOS18" loc="AE9" pcb_min_delay="0.38748" pcb_max_delay="0.47358"/>
<pin index="188" name ="som240_2_d31" iostandard="LVCMOS18" loc="AE8" pcb_min_delay="0.3874" pcb_max_delay="0.4735"/>
<pin index="189" name ="som240_2_d33" iostandard="LVCMOS18" oc="AC9" pcb_min_delay="0.39384" pcb_max_delay="0.48136"/>
<pin index="189" name ="som240_2_d33" iostandard="LVCMOS18" loc="AC9" pcb_min_delay="0.39384" pcb_max_delay="0.48136"/>
<pin index="190" name ="som240_2_d34" iostandard="LVCMOS18" loc="AD9" pcb_min_delay="0.39389" pcb_max_delay="0.48143"/>
<pin index="191" name ="som240_2_d36" iostandard="LVCMOS18" loc="AB8" pcb_min_delay="0.38799" pcb_max_delay="0.47421"/>
<pin index="192" name ="som240_2_d37" iostandard="LVCMOS18" loc="AC8" pcb_min_delay="0.38793" pcb_max_delay="0.47413"/>
......
FPGA/board/Macbeth/1.0/preset.xml
+ 346
− 352
View file @ ca8c38a2
......@@ -21,24 +21,51 @@
<!-- <user_parameter name="CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN" value="1" /> -->
<user_parameter name="CONFIG.PSU__PRESET_APPLIED" value="1"/>
<user_parameter name="CONFIG.PSU__UART1__PERIPHERAL__ENABLE" value="1"/>
<user_parameter name="CONFIG.PSU__UART1__PERIPHERAL__IO" value="MIO 36 .. 37"/>
<user_parameter name="CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL" value="IOPLL"/>
<user_parameter name="CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ" value="100"/>
<user_parameter name="CONFIG.PSU__ENET3__PERIPHERAL__ENABLE" value="1"/>
<user_parameter name="CONFIG.PSU__ENET3__PERIPHERAL__IO" value="MIO 64 .. 75"/>
<user_parameter name="CONFIG.PSU__ENET3__GRP_MDIO__ENABLE" value="1"/>
<user_parameter name="CONFIG.PSU__ENET3__GRP_MDIO__IO" value="MIO 76 .. 77"/>
<user_parameter name="CONFIG.PSU_MIO_71_PULLUPDOWN" value="disable"/>
<user_parameter name="CONFIG.PSU_MIO_73_PULLUPDOWN" value="disable"/>
<user_parameter name="CONFIG.PSU_MIO_75_PULLUPDOWN" value="disable"/>
<user_parameter name="CONFIG.PSU__SD1__PERIPHERAL__ENABLE" value="1"/>
<user_parameter name="CONFIG.PSU__SD1__DATA_TRANSFER_MODE" value="8Bit"/>
<user_parameter name="CONFIG.PSU__SD1__PERIPHERAL__IO" value="MIO 39 .. 51"/>
<user_parameter name="CONFIG.PSU__SD1__SLOT_TYPE" value="SD 3.0"/>
<user_parameter name="CONFIG.PSU__SD1__GRP_POW__ENABLE" value="1"/>
<user_parameter name="CONFIG.PSU__SD1__GRP_POW__IO" value="MIO 43"/>
<user_parameter name="CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL" value="IOPLL"/>
<user_parameter name="CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ" value="125"/>
<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__SRCSEL" value="IOPLL"/>
<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ" value="200"/>
<user_parameter name="CONFIG.PSU__SATA__REF_CLK_SEL" value="Ref Clk2"/>
<user_parameter name="CONFIG.PSU__SATA__REF_CLK_FREQ" value="125"/>
<user_parameter name="CONFIG.PSU__CRF_APB__SATA_REF_CTRL__SRCSEL" value="IOPLL"/>
<user_parameter name="CONFIG.PSU__CRF_APB__SATA_REF_CTRL__FREQMHZ" value="250"/>
<user_parameter name="CONFIG.PSU_BANK_0_IO_STANDARD" value="LVCMOS18"/>
<user_parameter name="CONFIG.PSU_BANK_1_IO_STANDARD" value="LVCMOS18"/>
<user_parameter name="CONFIG.PSU_BANK_2_IO_STANDARD" value="LVCMOS18"/>
<user_parameter name="CONFIG.PSU_BANK_3_IO_STANDARD" value="LVCMOS18"/>
<user_parameter name="CONFIG.PSU__CAN1__PERIPHERAL__ENABLE" value="0"/>
<user_parameter name="CONFIG.PSU__GPIO0_MIO__IO" value="MIO 0 .. 25"/>
<user_parameter name="CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE" value="1"/>
<!-- <user_parameter name="CONFIG.PSU__GPIO1_MIO__IO" value="MIO 26 .. 51"/>
<user_parameter name="CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE" value="1"/> -->
<user_parameter name="CONFIG.PSU__GPIO1_MIO__IO" value="MIO 26 .. 51"/>
<user_parameter name="CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE" value="1"/>
<user_parameter name="CONFIG.PSU__I2C0__PERIPHERAL__ENABLE" value="0"/>
<user_parameter name="CONFIG.PSU__I2C1__PERIPHERAL__ENABLE" value="1"/>
<user_parameter name="CONFIG.PSU__I2C1__PERIPHERAL__IO" value="MIO 24 .. 25"/>
<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__ENABLE" value="1"/>
<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE" value="x4"/>
<user_parameter name="CONFIG.PSU__QSPI__PERIPHERAL__IO" value="MIO 0 .. 5"/>
......@@ -48,21 +75,6 @@
<user_parameter name="CONFIG.PSU__SPI1__PERIPHERAL__ENABLE" value="1"/>
<user_parameter name="CONFIG.PSU__SPI1__GRP_SS1__ENABLE" value="0"/>
<user_parameter name="CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE" value="1"/>
<user_parameter name="CONFIG.PSU__DPAUX__PERIPHERAL__ENABLE" value="1"/>
<user_parameter name="CONFIG.PSU__DPAUX__PERIPHERAL__IO" value="MIO 27 .. 30"/>
<user_parameter name="CONFIG.PSU__DP__LANE_SEL" value="None"/>
<user_parameter name="CONFIG.PSU__SD0__DATA_TRANSFER_MODE" value="8Bit"/>
<user_parameter name="CONFIG.PSU__SD0__GRP_CD__ENABLE" value="0"/>
<user_parameter name="CONFIG.PSU__SD0__GRP_POW__ENABLE" value="1"/>
<user_parameter name="CONFIG.PSU__SD0__GRP_POW__IO" value="MIO 23"/>
<user_parameter name="CONFIG.PSU__SD0__GRP_WP__ENABLE" value="0"/>
<user_parameter name="CONFIG.PSU__SD0__PERIPHERAL__ENABLE" value="1"/>
<user_parameter name="CONFIG.PSU__SD0__PERIPHERAL__IO" value="MIO 13 .. 22"/>
<user_parameter name="CONFIG.PSU__SD0__RESET__ENABLE" value="1"/>
<user_parameter name="CONFIG.PSU__SD0__SLOT_TYPE" value="eMMC"/>
<user_parameter name="CONFIG.PSU__USE__IRQ0" value="1"/>
<user_parameter name="CONFIG.PSU__USE__M_AXI_GP0" value="1"/>
<user_parameter name="CONFIG.PSU__USE__M_AXI_GP1" value="1"/>
......@@ -262,12 +274,8 @@
<user_parameter name="CONFIG.PSU__DDRC__SELF_REF_ABORT" value="0"/>
<user_parameter name="CONFIG.PSU__PSS_REF_CLK__FREQMHZ" value="33.333"/>
<user_parameter name="CONFIG.PSU__DP__REF_CLK_FREQ" value="27"/>
<user_parameter name="CONFIG.PSU__DP__REF_CLK_SEL" value="Ref Clk0"/>
<user_parameter name="CONFIG.PSU__SATA__REF_CLK_SEL" value="Ref Clk2"/>
<user_parameter name="CONFIG.PSU__USB0__REF_CLK_SEL" value="Ref Clk1"/>
<user_parameter name="CONFIG.PSU__SATA__REF_CLK_FREQ" value="125"/>
<user_parameter name="CONFIG.PSU__USB0__REF_CLK_FREQ" value="26"/>
<user_parameter name="CONFIG.PSU__OVERRIDE__BASIC_CLOCK" value="0"/>
<user_parameter name="CONFIG.PSU__CRF_APB__APLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
<user_parameter name="CONFIG.PSU__CRF_APB__DPLL_CTRL__SRCSEL" value="PSS_REF_CLK"/>
......@@ -284,14 +292,8 @@
<user_parameter name="CONFIG.PSU__CRL_APB__SDIO1_REF_CTRL__FREQMHZ" value="200"/>
<user_parameter name="CONFIG.PSU__CRL_APB__UART0_REF_CTRL__SRCSEL" value="IOPLL"/>
<user_parameter name="CONFIG.PSU__CRL_APB__UART0_REF_CTRL__FREQMHZ" value="100"/>
<user_parameter name="CONFIG.PSU__CRL_APB__UART1_REF_CTRL__SRCSEL" value="IOPLL"/>
<user_parameter name="CONFIG.PSU__CRL_APB__UART1_REF_CTRL__FREQMHZ" value="100"/>
<user_parameter name="CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__SRCSEL" value="IOPLL"/>
<user_parameter name="CONFIG.PSU__CRL_APB__I2C0_REF_CTRL__FREQMHZ" value="100"/>
<user_parameter name="CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__SRCSEL" value="IOPLL"/>
<user_parameter name="CONFIG.PSU__CRL_APB__I2C1_REF_CTRL__FREQMHZ" value="100"/>
<user_parameter name="CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__SRCSEL" value="IOPLL"/>
<user_parameter name="CONFIG.PSU__CRL_APB__CAN1_REF_CTRL__FREQMHZ" value="100"/>
<user_parameter name="CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE" value="1"/>
<user_parameter name="CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE" value="1"/>
<user_parameter name="CONFIG.PSU__TTC0__PERIPHERAL__ENABLE" value="1"/>
......@@ -302,10 +304,6 @@
<user_parameter name="CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC2_SEL" value="APB"/>
<user_parameter name="CONFIG.PSU__TTC3__PERIPHERAL__ENABLE" value="1"/>
<user_parameter name="CONFIG.PSU__IOU_SLCR__IOU_TTC_APB_CLK__TTC3_SEL" value="APB"/>
<user_parameter name="CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__SRCSEL" value="IOPLL"/>
<user_parameter name="CONFIG.PSU__CRL_APB__USB0_BUS_REF_CTRL__FREQMHZ" value="250"/>
<user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__SRCSEL" value="IOPLL"/>
<user_parameter name="CONFIG.PSU__CRL_APB__USB3_DUAL_REF_CTRL__FREQMHZ" value="20"/>
<user_parameter name="CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__SRCSEL" value="IOPLL"/>
<user_parameter name="CONFIG.PSU__CRL_APB__GEM3_REF_CTRL__FREQMHZ" value="125"/>
<user_parameter name="CONFIG.PSU__FPGA_PL0_ENABLE" value="1"/>
......@@ -340,8 +338,6 @@
<user_parameter name="CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__SRCSEL" value="IOPLL"/>
<user_parameter name="CONFIG.PSU__CRL_APB__TIMESTAMP_REF_CTRL__FREQMHZ" value="100"/>
<user_parameter name="CONFIG.PSU__CRL_APB__PCAP_CTRL__SRCSEL" value="IOPLL"/>
<user_parameter name="CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL" value="RPLL"/>
<user_parameter name="CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL" value="RPLL"/>
<user_parameter name="CONFIG.PSU__CRL_APB__PCAP_CTRL__FREQMHZ" value="200"/>
<user_parameter name="CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__SRCSEL" value="IOPLL"/>
<user_parameter name="CONFIG.PSU__CRL_APB__ADMA_REF_CTRL__FREQMHZ" value="500"/>
......@@ -353,8 +349,6 @@
<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__FREQMHZ" value="533.33"/>
<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__SRCSEL" value="IOPLL"/>
<user_parameter name="CONFIG.PSU__CRF_APB__TOPSW_LSBUS_CTRL__FREQMHZ" value="100"/>
<user_parameter name="CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL" value="VPLL"/>
<user_parameter name="CONFIG.PSU__CRF_APB__GDMA_REF_CTRL__SRCSEL" value= "DPLL" />
<user_parameter name="CONFIG.PSU__CRL_APB__SPI1_REF_CTRL__SRCSEL" value= "IOPLL" />
......
FPGA/board/Macbeth/1.0/xitem.json
+ 2
− 2
View file @ ca8c38a2
......@@ -7,8 +7,8 @@
"display": "Macbeth Kria K26C SOM",
"revision": "1.0",
"description": "Macbeth Kria K26C SOM",
"company": "Synchrotron SOLEIL",
"company_display": "Synchrotron SOLEIL",
"company": "Synchrotron-SOLEIL",
"company_display": "Synchrotron-SOLEIL",
"author": "JP Ricaud ",
"contributors": [
{
......
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