From f630d7d8cd3add3a4e6e7142d99080b20a525e07 Mon Sep 17 00:00:00 2001 From: Romain Broucquart <romain.broucquart@synchrotron-soleil.fr> Date: Thu, 9 Mar 2023 10:11:18 +0100 Subject: [PATCH] fix(doc):Corrections on documentation, Module ID * Change module ID * Up to date wirh new phase incr/offs tables * Corrections on list --- doc/main.adoc | 43 +++++++++++++++++++++++++++++++++++++------ doc/registers.adoc | 3 ++- rdl/pscgen.rdl | 2 +- 3 files changed, 40 insertions(+), 8 deletions(-) diff --git a/doc/main.adoc b/doc/main.adoc index 779a015..618b8c4 100644 --- a/doc/main.adoc +++ b/doc/main.adoc @@ -1,5 +1,9 @@ = Power Supply Controller Generator +|=== +| MODULE ID | 0x507E1712 | (1350440722) +|=== + // ================================================================================ == Description This module can generate sine waveform for multiple power supplies. @@ -10,6 +14,7 @@ The TUSER output carries the Identifier of the waveform. It is possible to generate up to `2**C_W_TIDX` (default 255) Identifiers. Each waveform has independents parameters: + * Phase increment * Phase offset * Scaling value @@ -25,18 +30,24 @@ The values are output via the AXI-Stream Output, one value transaction by transf The generator will compute and ouput values for Identifier from `TABLE_DEPTH` downto 0. Entries in the `TABLE_PHASE` and `TABLE_SCALE` for these Identifier shall be configured by the user. These two tables are addressed by the Identifier number. -Data values pack configuration, as descrived below. +Data values pack configuration, as described below. -.TABLE_PHASE data pack. +.TABLE_PHASE_INCR data pack. |=== -| `31-2*C_W_PHASE` bits |1 bit | `C_W_PHASE` bits | `C_W_PHASE` bits | -| unused |Reset accumulator | Phase offset | Phase increment | +| `32-C_W_PHASE` bits | `C_W_PHASE` bits +| unused | Phase increment +|=== + +.TABLE_PHASE_OFFS data pack. +|=== +| `31-*C_W_PHASE` bits |1 bit | `C_W_PHASE` bits +| unused |Reset accumulator | Phase offset |=== .TABLE_SCALE data pack. |=== -| `32-C_W_OFFSET-C_W_SCALE` bits | `C_W_OFFSET` bits | `C_W_SCALE` bits | -| unused | Signal Offset | Signal Scale Factor | +| `32-C_W_OFFSET-C_W_SCALE` bits | `C_W_OFFSET` bits | `C_W_SCALE` bits +| unused | Signal Offset | Signal Scale Factor |=== The DDS contained in the module receive the phase value, computed from the sum of the accumulator and the *Phase Offset* configuration. @@ -48,7 +59,27 @@ The output of the DDS is multiplied by the *Signal Scale Factor*, which is consi The *Signal Offset* is then applied, aligned on the fixed point (no decimals). The final result is scrapped of decimals values. +// ================================================================================ +== AXIS output format +The generator produces AXIS packets with a compatible format for COMCORR IP module. + +The AXIS contains: + +* TDATA: the sine waveform value (signed integer). +* TUSER: the PSCID. +* TVALID: data strobe. + +The AXIS **does not** contain **TREADY** input on this module. +The COMCORR IP module does not either. // ================================================================================ == Registers map include::registers.adoc[] + + +// ================================================================================ +== TODO / Future devs + +* The PSCID is now a simple count down from `TABLE_DEPTH` to 0. + A table to translate from this count to a proper PSCID will be implemented. + In the meantime, a correct configuration of the COMCORR module shall suffice. diff --git a/doc/registers.adoc b/doc/registers.adoc index 9bdd627..782a493 100644 --- a/doc/registers.adoc +++ b/doc/registers.adoc @@ -15,7 +15,8 @@ |=== |Name | N | bits | type | RW | Description -| TABLE_PHASE | 256 | 31 | uint | RW | +++Phase increment and offset table+++ +| TABLE_PHASE_INCR | 256 | 31 | uint | RW | +++Phase increment table+++ +| TABLE_PHASE_OFFS | 256 | 31 | uint | RW | +++Phase offset and reset table+++ | TABLE_SCALE | 256 | 32 | uint | RW | +++Signal scale and offset table+++ |=== diff --git a/rdl/pscgen.rdl b/rdl/pscgen.rdl index cc58ae7..885ce6e 100644 --- a/rdl/pscgen.rdl +++ b/rdl/pscgen.rdl @@ -2,7 +2,7 @@ /* default values of defined variables */ `ifndef C_ID -`define C_ID 0x1FF00002 +`define C_ID 0x507E1712 `endif `ifndef C_VERSION `define C_VERSION 0x00000000 -- GitLab