From 1782b8d23fbb3b7058a9b935b059ec5f7205e90a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Romain=20Bron=C3=A8s?= <romain.brones@synchrotron-soleil.fr>
Date: Tue, 21 Mar 2023 16:12:36 +0100
Subject: [PATCH] feat(ddr):Add PL DDR to device-tree

* Usefull when we do not use DT_FROM_BD
---
 .../device-tree/files/damc-fmc2zup/pl-conf.dtsi  | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/recipes-bsp/device-tree/files/damc-fmc2zup/pl-conf.dtsi b/recipes-bsp/device-tree/files/damc-fmc2zup/pl-conf.dtsi
index 00cfcd4..439f775 100644
--- a/recipes-bsp/device-tree/files/damc-fmc2zup/pl-conf.dtsi
+++ b/recipes-bsp/device-tree/files/damc-fmc2zup/pl-conf.dtsi
@@ -1,6 +1,22 @@
 
 
 / {
+	amba_pl: amba_pl@0 {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		compatible = "simple-bus";
+		ranges ;
+		ddr_ddr4_0: ddr4@540000000 {
+			compatible = "xlnx,ddr4-2.2", "generic-uio";
+			reg = <0x00000005 0x40000000 0x0 0x40000000>;
+		};
+		ins_bsp_fmc2zup_system_p_m_axi_bsp: ins_bsp_fmc2zup_system_p_m_axi_bsp@a0000000 {
+			reg = <0x0 0xa0000000 0x0 0x200000>;
+		};
+		ins_bsp_fmc2zup_system_p_m_axi_app: ins_bsp_fmc2zup_system_p_m_axi_app@a0800000 {
+			reg = <0x0 0xa0800000 0x0 0x800000>;
+		};
+	};
 
     debug_bridge_0@0xA0820000 {
         #address-cells = <1>;
-- 
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