From a1355d66598de22321806d16cf3840cfe147739c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Romain=20Bron=C3=A8s?= <romain.brones@synchrotron-soleil.fr>
Date: Fri, 5 Jul 2024 17:28:01 +0200
Subject: [PATCH] fix(sim): Align testbench to sim data files
* Also I had a nasty GHDL error that was solved by this, not sure why...
---
sim/tc_basic.vhd | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/sim/tc_basic.vhd b/sim/tc_basic.vhd
index 86fe3eb..5fff9c0 100644
--- a/sim/tc_basic.vhd
+++ b/sim/tc_basic.vhd
@@ -91,20 +91,20 @@ begin
log("+-- Global Config", INFO);
-- Correction coefficients
- Write(ManagerRec, f_addr(16#18#), f_sdata(218));
- Write(ManagerRec, f_addr(16#1C#), f_sdata(-186));
- Write(ManagerRec, f_addr(16#20#), f_sdata(325));
- Write(ManagerRec, f_addr(16#24#), f_sdata(-3225));
- Write(ManagerRec, f_addr(16#38#), f_sdata(218));
- Write(ManagerRec, f_addr(16#3C#), f_sdata(-186));
- Write(ManagerRec, f_addr(16#40#), f_sdata(325));
- Write(ManagerRec, f_addr(16#44#), f_sdata(-3225));
-
- Write(ManagerRec, f_addr(16#28#), f_sdata(128));
+ Write(ManagerRec, f_addr(16#18#), f_sdata(256));
+ Write(ManagerRec, f_addr(16#1C#), f_sdata(0));
+ Write(ManagerRec, f_addr(16#20#), f_sdata(64));
+ Write(ManagerRec, f_addr(16#24#), f_sdata(-16300));
+ Write(ManagerRec, f_addr(16#38#), f_sdata(256));
+ Write(ManagerRec, f_addr(16#3C#), f_sdata(0));
+ Write(ManagerRec, f_addr(16#40#), f_sdata(64));
+ Write(ManagerRec, f_addr(16#44#), f_sdata(-16300));
+
+ Write(ManagerRec, f_addr(16#28#), f_sdata(32768));
Write(ManagerRec, f_addr(16#2C#), f_sdata(0));
Write(ManagerRec, f_addr(16#30#), f_sdata(8192));
Write(ManagerRec, f_addr(16#34#), f_sdata(0));
- Write(ManagerRec, f_addr(16#48#), f_sdata(128));
+ Write(ManagerRec, f_addr(16#48#), f_sdata(32768));
Write(ManagerRec, f_addr(16#4C#), f_sdata(0));
Write(ManagerRec, f_addr(16#50#), f_sdata(8192));
Write(ManagerRec, f_addr(16#54#), f_sdata(0));
@@ -151,7 +151,7 @@ begin
for I in 0 to C_N_MM_BPM-1 loop
readline(read_file, line_v);
read(line_v, int_v);
- Write(ManagerRec, f_addr(16#1000#+J*512+I*4), f_sdata(int_v));
+ Write(ManagerRec, f_addr(16#1000#+J*1024+I*4), f_sdata(int_v));
end loop;
end loop;
--
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