From 8fbf5586d3b527de042a8336b9637343006f96c7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Romain=20Bron=C3=A8s?= <romain.brones@synchrotron-soleil.fr> Date: Mon, 30 Oct 2023 14:30:03 +0100 Subject: [PATCH] fix(sim): Fiw simulation to match two correctors * Update register address * Configure second register as unitary --- sim/generate_datasim.py | 12 ++++++++++-- sim/tc_basic.vhd | 19 ++++++++++++++----- 2 files changed, 24 insertions(+), 7 deletions(-) diff --git a/sim/generate_datasim.py b/sim/generate_datasim.py index b7564db..9d32158 100644 --- a/sim/generate_datasim.py +++ b/sim/generate_datasim.py @@ -65,13 +65,21 @@ with open("bpmdata.txt", "w") as fp: trespmat = np.zeros((N_PSC, N_BPM), dtype="int64") trespmat[:50,:122] = respmat[:50] trespmat[50:,122:] = respmat[50:] +C_N_RND = 20 +SUMSAT=36 + K_A = 218 K_B = -186 K_iC = 325 K_D = -3225 -C_N_RND = 26 -SUMSAT=36 + + +K_A = 1024 +K_B = 0 +K_iC = 1024 +K_D = 0 + ## ----------------------- # Model computation diff --git a/sim/tc_basic.vhd b/sim/tc_basic.vhd index 31ad508..9a6deb7 100644 --- a/sim/tc_basic.vhd +++ b/sim/tc_basic.vhd @@ -88,14 +88,23 @@ begin log("==--- Configure the DUT ---==", INFO); log("+-- Global Config", INFO); + -- Correction coefficients - Write(ManagerRec, f_addr(16#0C#), f_sdata(218)); - Write(ManagerRec, f_addr(16#10#), f_sdata(-186)); - Write(ManagerRec, f_addr(16#14#), f_sdata(325)); - Write(ManagerRec, f_addr(16#18#), f_sdata(-3225)); + Write(ManagerRec, f_addr(16#10#), f_sdata(218)); + Write(ManagerRec, f_addr(16#14#), f_sdata(-186)); + Write(ManagerRec, f_addr(16#18#), f_sdata(325)); + Write(ManagerRec, f_addr(16#1C#), f_sdata(-3225)); + + Write(ManagerRec, f_addr(16#20#), f_sdata(128)); + Write(ManagerRec, f_addr(16#24#), f_sdata(0)); + Write(ManagerRec, f_addr(16#28#), f_sdata(8192)); + Write(ManagerRec, f_addr(16#2C#), f_sdata(0)); + + -- Rst corr and threshold + Write(ManagerRec, f_addr(8), f_sdata(10)); -- Enable - Write(ManagerRec, f_addr(8), f_sdata(5)); + Write(ManagerRec, f_addr(8), f_sdata(1)); log("+-- Writing orbit reference...", INFO); -- GitLab