From 7ff3bbb1db8193d6fad173824701fd9750768191 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Romain=20Bron=C3=A8s?= <romain.brones@synchrotron-soleil.fr>
Date: Thu, 1 Jun 2023 09:41:50 +0200
Subject: [PATCH] Behavioral fixes on valid signals
* Fix delay on matmul valid signal
* Fix length of validity for correction output
---
hdl/data_serializer.vhd | 2 +-
hdl/matrix_mul.vhd | 5 ++++-
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/hdl/data_serializer.vhd b/hdl/data_serializer.vhd
index 040fe00..6592884 100644
--- a/hdl/data_serializer.vhd
+++ b/hdl/data_serializer.vhd
@@ -80,7 +80,7 @@ begin
if corrout_valid= '1' then
-- start on valid
run_serial <= '1';
- cnt <= to_unsigned(C_N_MM_PSC, cnt'length);
+ cnt <= to_unsigned(C_N_MM_PSC-1, cnt'length);
end if;
diff --git a/hdl/matrix_mul.vhd b/hdl/matrix_mul.vhd
index dacbc77..c410766 100644
--- a/hdl/matrix_mul.vhd
+++ b/hdl/matrix_mul.vhd
@@ -58,6 +58,7 @@ architecture rtl of matrix_mul is
signal new_seq : std_logic;
signal mul_done : std_logic;
+ signal r_mul_done : std_logic;
begin
@@ -101,7 +102,9 @@ begin
if rst_n = '0' then
id_cnt <= (others => '1');
mul_done <= '0';
+ r_mul_done <= '0';
elsif rising_edge(clk) then
+ r_mul_done <= mul_done;
if id_cnt = 0 then
id_cnt <= unsigned(id_cnt_load);
mul_done <= '1';
@@ -217,7 +220,7 @@ begin
--------------------
-- OUTPUT CONNECT --
--------------------
- matmult_tvalid <= mul_done;
+ matmult_tvalid <= r_mul_done;
matmult_seq <= r_seq;
end architecture;
--
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