From 4e0309f9f4ab2edbd4a825319966a31bd5c1830b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Romain=20Bron=C3=A8s?= <romain.brones@synchrotron-soleil.fr>
Date: Wed, 7 Jun 2023 17:55:22 +0200
Subject: [PATCH] fix: Add pipeline stage, remove tready
* PSCID memory read require one clock tick, so add a pipeline stage
* To limit complexity, remove tready. Throttling will be done outside
---
hdl/data_serializer.vhd | 28 ++++++++++++++--------------
hdl/top_corr_matrixpi.vhd | 7 ++-----
sim/tb_corr_matrixpi.vhd | 3 +--
3 files changed, 17 insertions(+), 21 deletions(-)
diff --git a/hdl/data_serializer.vhd b/hdl/data_serializer.vhd
index 6323b76..6e5c762 100644
--- a/hdl/data_serializer.vhd
+++ b/hdl/data_serializer.vhd
@@ -31,8 +31,7 @@ entity data_serializer is
-- AXIS serial output
m_axis_tdata : out std_logic_vector(C_W_COR+C_W_PSCID-1 downto 0);
m_axis_tuser : out std_logic_vector(C_W_BPMSEQ-1 downto 0);
- m_axis_tvalid : out std_logic;
- m_axis_tready : in std_logic
+ m_axis_tvalid : out std_logic
);
end entity data_serializer;
@@ -44,10 +43,11 @@ architecture rtl of data_serializer is
------------------------
signal cnt : unsigned(C_W_SER_CNT-1 downto 0);
signal run_serial : std_logic;
+ signal r_run_serial : std_logic;
signal pscid : std_logic_vector(C_W_PSCID-1 downto 0);
- signal r_corr : signed_array(0 to C_N_MM_PSC-1)(C_W_COR-1 downto 0);
+ signal r_corr : signed_array(0 to C_N_MM_PSC)(C_W_COR-1 downto 0);
signal r_seq : std_logic_vector(C_W_BPMSEQ-1 downto 0);
begin
@@ -60,19 +60,20 @@ begin
if rst_n = '0' then
cnt <= (others => '0');
run_serial <= '0';
+ r_run_serial<= '0';
overrun <= '0';
elsif rising_edge(clk) then
+ r_run_serial <= run_serial;
if run_serial = '1' then
if cnt = C_N_MM_PSC-1 then
-- stop at the end
run_serial <= '0';
else
- if m_axis_tready = '1' then
- cnt <= cnt+1;
- end if;
+ cnt <= cnt+1;
end if;
+
-- Transmit overrun if a valid comes here
overrun <= corrout_valid;
@@ -99,15 +100,14 @@ begin
r_corr <= (others => (others => '0'));
r_seq <= (others => '0');
elsif rising_edge(clk) then
+ r_corr(0) <= r_corr(1);
if run_serial = '1' then
- if m_axis_tready = '1' then
- for I in 0 to C_N_MM_PSC-2 loop
- r_corr(I) <= r_corr(I+1);
- end loop;
- end if;
+ for I in 1 to C_N_MM_PSC-1 loop
+ r_corr(I) <= r_corr(I+1);
+ end loop;
else
- r_corr <= corrout;
- r_seq <= corrout_seq;
+ r_corr(1 to C_N_MM_PSC) <= corrout;
+ r_seq <= corrout_seq;
end if;
end if;
end process;
@@ -142,7 +142,7 @@ begin
-----------------------
m_axis_tdata <= pscid & std_logic_vector(r_corr(0));
m_axis_tuser <= r_seq;
- m_axis_tvalid <= run_serial;
+ m_axis_tvalid <= r_run_serial;
end architecture;
diff --git a/hdl/top_corr_matrixpi.vhd b/hdl/top_corr_matrixpi.vhd
index e52abc7..c65a30a 100644
--- a/hdl/top_corr_matrixpi.vhd
+++ b/hdl/top_corr_matrixpi.vhd
@@ -25,9 +25,7 @@ entity top_corr_matrixpi is
-- AXIS output
m_axis_tdata : out std_logic_vector(C_W_COR+C_W_PSCID-1 downto 0);
m_axis_tuser : out std_logic_vector(C_W_BPMSEQ-1 downto 0);
- m_axis_tvalid : out std_logic;
- m_axis_tready : in std_logic
-
+ m_axis_tvalid : out std_logic
);
end entity;
@@ -203,8 +201,7 @@ begin
-- AXIS serial output
m_axis_tdata => m_axis_tdata,
m_axis_tuser => m_axis_tuser,
- m_axis_tvalid => m_axis_tvalid,
- m_axis_tready => m_axis_tready
+ m_axis_tvalid => m_axis_tvalid
);
diff --git a/sim/tb_corr_matrixpi.vhd b/sim/tb_corr_matrixpi.vhd
index 17bee12..a82d6fb 100644
--- a/sim/tb_corr_matrixpi.vhd
+++ b/sim/tb_corr_matrixpi.vhd
@@ -135,8 +135,7 @@ begin
-- AXIS output
m_axis_tdata => tb_axis_rx_tdata,
m_axis_tuser => tb_axis_rx_tuser,
- m_axis_tvalid => tb_axis_rx_tvalid,
- m_axis_tready => tb_axis_rx_tready
+ m_axis_tvalid => tb_axis_rx_tvalid
);
--
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