-- PROJECT FOFB
-- COMBPM ELECTRON TOP LEVEL
-- RBR
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library xpm;
use xpm.vcomponents.all;
library desyrdl;
use desyrdl.common.all;
use desyrdl.pkg_combpm.all;
use work.pkg_bpmpacket_stream.all;
use work.pkg_combpm_version.all;
entity top_combpm_electron is
port(
rst_n : in std_logic; -- Asynchronous reset
free_100_clk : in std_logic; -- Freerunning clock for GT
pps : in std_logic; -- A pulse per second signal, sync to clk domain
clk : out std_logic; -- main clock (AXIS and AXI-MM)
mc_time : in std_logic_vector(39 downto 0);
-- Transceiver QPLL interface
qpll_out_clk : in std_logic; -- QPLL clock for transceivers
qpll_ref_clk : in std_logic; -- QPLL ref clock
qpll_reset : out std_logic; -- QPLL reset
qpll_lock : in std_logic; -- QPLL is locked
-- Debug output
debug_datarx : out std_logic_vector(15 downto 0);
debug_status : out std_logic_vector(6 downto 0);
error_detect : out std_logic;
-- SFP interfaces
sfp_txp : out std_logic;
sfp_txn : out std_logic;
sfp_rxp : in std_logic;
sfp_rxn : in std_logic;
sfp_rx_los : in std_logic;
sfp_mod_abs : in std_logic;
sfp_tx_disable : out std_logic;
sfp_tx_fault : in std_logic;
-- AXIS interface
m_axis_m2s : out t_bpmpacket_axis_m2s;
m_axis_s2m : in t_bpmpacket_axis_s2m; -- warning: TREADY is ignored !
-- AXI bus interface
pi_s_top : in t_COMBPM_m2s;
po_s_top : out t_COMBPM_s2m
);
end top_combpm_electron;
architecture struct of top_combpm_electron is
COMPONENT combpm_gtwizard
PORT (
gtwiz_userclk_tx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_tx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userclk_rx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_qpll1lock_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_reset_qpll1reset_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
gthrxn_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
gthrxp_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll0clk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll0refclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1clk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
qpll1refclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rx8b10ben_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rxbufreset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rxcommadeten_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rxmcommaalignen_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
rxpcommaalignen_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
tx8b10ben_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
txctrl0_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
txctrl1_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
txctrl2_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
gthtxn_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gthtxp_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
gtpowergood_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxbufstatus_out : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
rxbyteisaligned_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxbyterealign_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxcdrlock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxclkcorcnt_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
rxcommadet_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
rxctrl0_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rxctrl1_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
rxctrl2_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rxctrl3_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
txpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
);
END COMPONENT;
------------------------
-- SIGNAL DECLARATION --
------------------------
signal sync_resetn : std_logic; -- This is async reset with sync deassertion
signal sync_reset : std_logic; -- This is async reset with sync deassertion
signal usrclk : std_logic;
signal rst : std_logic;
signal frame_seq_cnt : std_logic_vector(15 downto 0);
signal frame_valid_cnt : std_logic_vector(31 downto 0);
signal frame_invalid_cnt : std_logic_vector(31 downto 0);
signal frame_valid_rate : std_logic_vector(31 downto 0);
signal frame_invalid_rate : std_logic_vector(31 downto 0);
signal cnt_seq_mismatch : std_logic;
signal seq_discontinuity : std_logic;
signal frame_error : std_logic;
signal gt_datarx : std_logic_vector(15 downto 0);
signal gt_powergood : std_logic;
signal gt_rxcdrlock : std_logic;
signal gt_rxresetdone : std_logic;
signal gt_rxbyteisaligned : std_logic;
signal gt_rxbyterealign : std_logic;
signal gt_rxcommadet : std_logic;
signal addrmap_w : t_addrmap_combpm_in;
signal addrmap_r : t_addrmap_combpm_out;
begin
-- This CDC is used to deassert async reset in sync with the transceiver clock.
xpm_cdc_async_rst_inst : xpm_cdc_async_rst
generic map (
DEST_SYNC_FF => 4,
INIT_SYNC_FF => 0,
RST_ACTIVE_HIGH => 0 -- DECIMAL; 0=active low reset, 1=active high reset
)
port map (
dest_arst => sync_resetn,
dest_clk => usrclk,
src_arst => rst_n
);
-- Reset invert polarity
rst <= not rst_n;
sync_reset <= not sync_resetn;
-- Debug
debug_datarx <= gt_datarx;
debug_status(0) <= gt_rxcommadet;
debug_status(1) <= gt_rxcdrlock;
debug_status(2) <= gt_rxbyterealign;
debug_status(3) <= gt_rxbyteisaligned;
debug_status(4) <= frame_error;
debug_status(5) <= cnt_seq_mismatch;
debug_status(6) <= seq_discontinuity;
error_detect <= frame_error or cnt_seq_mismatch or seq_discontinuity;
-- Output clock
clk <= usrclk;
-- SFP direct connexion
sfp_tx_disable <= '1';
----------------------
-- AXI-MM INTERFACE --
----------------------
blk_desyrdl: block
begin
inst_aximm: entity desyrdl.combpm
port map(
pi_clock => usrclk,
pi_reset => sync_reset,
pi_s_top => pi_s_top,
po_s_top => po_s_top,
pi_addrmap => addrmap_w,
po_addrmap => addrmap_r
);
addrmap_w.ID.data.data <= x"507E1710";
addrmap_w.VERSION.data.data <= C_VERSION;
addrmap_w.SFP.RXLOS.data(0) <= sfp_rx_los;
addrmap_w.SFP.MODABS.data(0) <= sfp_mod_abs;
addrmap_w.GT.POWERGOOD.data(0) <= gt_powergood;
addrmap_w.GT.QPLLLOCK.data(0) <= qpll_lock;
addrmap_w.GT.RXCDRLOCK.data(0) <= gt_rxcdrlock;
addrmap_w.GT.RXRESETDONE.data(0) <= gt_rxresetdone;
addrmap_w.GT.RXBYTEISALIGNED.data(0) <= gt_rxbyteisaligned;
addrmap_w.GT.RXBYTEREALIGN.data(0) <= gt_rxbyterealign;
addrmap_w.GT.RXCOMMADET.data(0) <= gt_rxcommadet;
addrmap_w.PROTOCOL.FRAMEERROR.data(0) <= frame_error;
addrmap_w.PROTOCOL.SEQFRAMECNTERROR.data(0) <= cnt_seq_mismatch;
addrmap_w.PROTOCOL.SEQFRAMEDISCONT.data(0) <= seq_discontinuity;
addrmap_w.VALIDFRAMECNT.data.data <= frame_valid_cnt;
addrmap_w.INVALIDFRAMECNT.data.data <= frame_invalid_cnt;
addrmap_w.VALIDFRAMERATE.data.data <= frame_valid_rate;
addrmap_w.INVALIDFRAMERATE.data.data <= frame_invalid_rate;
addrmap_w.FRAMESEQ.data.data <= frame_seq_cnt;
end block blk_desyrdl;
--------------------------------------
-- LIBERA ELECTRON PROCOTOL DECODER --
--------------------------------------
protocol_inst: entity work.combpm_protocol_electron
port map(
rst_n => sync_resetn,
clk => usrclk,
pps => pps,
gt_datarx => gt_datarx,
m_axis_m2s => m_axis_m2s,
m_axis_s2m => m_axis_s2m,
mc_time => mc_time,
soft_reset => addrmap_w.PROTOCOL.SOFTRESET.data(0),
frame_seq_cnt => frame_seq_cnt,
frame_valid_cnt => frame_valid_cnt,
frame_invalid_cnt => frame_invalid_cnt,
frame_valid_rate => frame_valid_rate,
frame_invalid_rate => frame_invalid_rate,
cnt_seq_mismatch => cnt_seq_mismatch,
seq_discontinuity => seq_discontinuity,
frame_error => frame_error
);
---------------
-- GT WIZARD --
---------------
gtwizard_inst : combpm_gtwizard
PORT MAP (
-- Async reset
gtwiz_reset_all_in(0) => rst,
gtwiz_userclk_tx_reset_in(0) => rst,
gtwiz_userclk_rx_reset_in(0) => rst,
-- Free run clock
gtwiz_reset_clk_freerun_in(0) => free_100_clk,
-- Clock and data
gtwiz_userclk_rx_usrclk2_out(0) => usrclk,
gtwiz_userdata_tx_in => (others => '0'),
gtwiz_userdata_rx_out => gt_datarx,
-- QPLL COMMON
gtwiz_reset_qpll1lock_in(0) => qpll_lock,
gtwiz_reset_qpll1reset_out(0) => qpll_reset,
qpll1clk_in(0) => qpll_out_clk,
qpll1refclk_in(0) => qpll_ref_clk,
-- Control
gtwiz_reset_rx_datapath_in => addrmap_r.GT.RXRSTDATAPATH.data,
gtwiz_reset_rx_pll_and_datapath_in => addrmap_r.GT.RXRSTPLLDATAPATH.data,
rxbufreset_in => "0",
rxcommadeten_in => addrmap_r.GT.RXCOMMADETEN.data,
rx8b10ben_in => "1",
rxmcommaalignen_in => "1",
rxpcommaalignen_in => "1",
tx8b10ben_in => "1",
gtwiz_reset_tx_pll_and_datapath_in => "0",
gtwiz_reset_tx_datapath_in => "0",
-- Status
gtwiz_userclk_tx_active_out => open,
gtwiz_userclk_rx_active_out => addrmap_w.GT.RXCLKACTIVE.data,
gtwiz_reset_tx_done_out => open,
gtwiz_reset_rx_done_out(0) => gt_rxresetdone,
gtpowergood_out(0) => gt_powergood,
rxbyteisaligned_out(0) => gt_rxbyteisaligned,
rxbyterealign_out(0) => gt_rxbyterealign,
rxcdrlock_out(0) => gt_rxcdrlock,
rxcommadet_out(0) => gt_rxcommadet,
rxbufstatus_out => open,
rxclkcorcnt_out => open,
rxpmaresetdone_out => open,
txpmaresetdone_out => open,
-- SFP
gthrxn_in(0) => sfp_rxn,
gthrxp_in(0) => sfp_rxp,
gthtxn_out(0) => sfp_txn,
gthtxp_out(0) => sfp_txp,
-- Not used
qpll0clk_in => "0", -- not used
qpll0refclk_in => "0", -- not used
gtwiz_reset_rx_cdr_stable_out => open, -- Do not use
gtwiz_userclk_rx_srcclk_out => open,
gtwiz_userclk_rx_usrclk_out => open,
rxctrl0_out => open,
rxctrl1_out => open,
rxctrl2_out => open,
rxctrl3_out => open,
txctrl0_in => (others => '0'),
txctrl1_in => (others => '0'),
txctrl2_in => (others => '0'),
gtwiz_userclk_tx_srcclk_out => open,
gtwiz_userclk_tx_usrclk_out => open,
gtwiz_userclk_tx_usrclk2_out => open
);
end architecture struct;