diff --git a/hdl/pkg_combpm.vhd b/hdl/pkg_combpm.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..67c7acb6d2e488d69ef1bff59f1aa4917aeb7e08
--- /dev/null
+++ b/hdl/pkg_combpm.vhd
@@ -0,0 +1,71 @@
+
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package pkg_combpm is
+
+
+ -------------------------
+ -- GT WIZARD COMPONENT --
+ -------------------------
+ COMPONENT combpm_gtwizard
+ PORT (
+ gtwiz_userclk_tx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userclk_tx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userclk_tx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userclk_tx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userclk_tx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userclk_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userclk_rx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userclk_rx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userclk_rx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userclk_rx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_qpll1lock_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_reset_qpll1reset_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+ gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ gthrxn_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gthrxp_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ qpll0clk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ qpll0refclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ qpll1clk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ qpll1refclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rx8b10ben_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rxbufreset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rxcommadeten_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rxmcommaalignen_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rxpcommaalignen_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ tx8b10ben_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
+ txctrl0_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+ txctrl1_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
+ txctrl2_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+ gthtxn_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gthtxp_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ gtpowergood_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rxbufstatus_out : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
+ rxbyteisaligned_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rxbyterealign_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rxcdrlock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rxclkcorcnt_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
+ rxcommadet_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ rxctrl0_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ rxctrl1_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+ rxctrl2_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ rxctrl3_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+ rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
+ txpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
+ );
+ END COMPONENT;
+
+end package;
\ No newline at end of file
diff --git a/hdl/top_combpm_electron.vhd b/hdl/top_combpm_electron.vhd
index 505ff0f6ea2afe439679617a624005514381b8d9..b4e6831e04220005bcbb273786fa5991efd6f7fd 100644
--- a/hdl/top_combpm_electron.vhd
+++ b/hdl/top_combpm_electron.vhd
@@ -15,6 +15,7 @@ use desyrdl.pkg_combpm.all;
use work.pkg_bpmpacket_stream.all;
use work.pkg_combpm_version.all;
+use work.pkg_combpm.all;
entity top_combpm_electron is
port(
@@ -22,7 +23,6 @@ entity top_combpm_electron is
rst_n : in std_logic; -- Asynchronous reset
free_100_clk : in std_logic; -- Freerunning clock for GT
pps : in std_logic; -- A pulse per second signal, sync to clk domain
- clk : out std_logic; -- main clock (AXIS and AXI-MM)
mc_time : in std_logic_vector(39 downto 0);
-- Transceiver QPLL interface
@@ -47,75 +47,19 @@ entity top_combpm_electron is
sfp_tx_fault : in std_logic;
-- AXIS interface
+ m_axis_aclk : out std_logic;
m_axis_m2s : out t_bpmpacket_axis_m2s;
m_axis_s2m : in t_bpmpacket_axis_s2m; -- warning: TREADY is ignored !
-- AXI bus interface
- pi_s_top : in t_COMBPM_m2s;
- po_s_top : out t_COMBPM_s2m
+ s_axi_aclk : in std_logic;
+ pi_s_top : in t_combpm_m2s;
+ po_s_top : out t_combpm_s2m
);
end top_combpm_electron;
architecture struct of top_combpm_electron is
- COMPONENT combpm_gtwizard
- PORT (
- gtwiz_userclk_tx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_userclk_tx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_userclk_tx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_userclk_tx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_userclk_tx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_userclk_rx_reset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_userclk_rx_srcclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_userclk_rx_usrclk_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_userclk_rx_usrclk2_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_userclk_rx_active_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_clk_freerun_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_all_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_tx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_tx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_rx_pll_and_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_rx_datapath_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_qpll1lock_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_rx_cdr_stable_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_tx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_rx_done_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_reset_qpll1reset_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtwiz_userdata_tx_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
- gtwiz_userdata_rx_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
- gthrxn_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- gthrxp_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- qpll0clk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- qpll0refclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- qpll1clk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- qpll1refclk_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- rx8b10ben_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- rxbufreset_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- rxcommadeten_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- rxmcommaalignen_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- rxpcommaalignen_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- tx8b10ben_in : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
- txctrl0_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
- txctrl1_in : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
- txctrl2_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
- gthtxn_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- gthtxp_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- gtpowergood_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- rxbufstatus_out : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
- rxbyteisaligned_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- rxbyterealign_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- rxcdrlock_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- rxclkcorcnt_out : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
- rxcommadet_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- rxctrl0_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
- rxctrl1_out : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
- rxctrl2_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
- rxctrl3_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
- rxpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
- txpmaresetdone_out : OUT STD_LOGIC_VECTOR(0 DOWNTO 0)
- );
- END COMPONENT;
-
------------------------
-- SIGNAL DECLARATION --
------------------------
@@ -144,6 +88,12 @@ architecture struct of top_combpm_electron is
signal addrmap_w : t_addrmap_combpm_in;
signal addrmap_r : t_addrmap_combpm_out;
+ signal cdc_status_array_axi : std_logic_vector(155 downto 0); -- CDC, clock axi side
+ signal cdc_status_array_bpm : std_logic_vector(155 downto 0); -- CDC, clock bpm side
+ signal cdc_control_array_axi : std_logic_vector(2 downto 0); -- CDC, clock axi side
+ signal cdc_control_array_bpm : std_logic_vector(2 downto 0); -- CDC, clock bpm side
+
+
begin
@@ -177,7 +127,7 @@ begin
error_detect <= frame_error or cnt_seq_mismatch or seq_discontinuity;
-- Output clock
- clk <= usrclk;
+ m_axis_aclk <= usrclk;
-- SFP direct connexion
sfp_tx_disable <= '1';
@@ -189,7 +139,7 @@ begin
begin
inst_aximm: entity desyrdl.combpm
port map(
- pi_clock => usrclk,
+ pi_clock => s_axi_aclk,
pi_reset => sync_reset,
pi_s_top => pi_s_top,
po_s_top => po_s_top,
@@ -197,30 +147,80 @@ begin
po_addrmap => addrmap_r
);
-
addrmap_w.ID.data.data <= x"507E1710";
addrmap_w.VERSION.data.data <= C_VERSION;
- addrmap_w.SFP.RXLOS.data(0) <= sfp_rx_los;
- addrmap_w.SFP.MODABS.data(0) <= sfp_mod_abs;
-
- addrmap_w.GT.POWERGOOD.data(0) <= gt_powergood;
- addrmap_w.GT.QPLLLOCK.data(0) <= qpll_lock;
- addrmap_w.GT.RXCDRLOCK.data(0) <= gt_rxcdrlock;
- addrmap_w.GT.RXRESETDONE.data(0) <= gt_rxresetdone;
- addrmap_w.GT.RXBYTEISALIGNED.data(0) <= gt_rxbyteisaligned;
- addrmap_w.GT.RXBYTEREALIGN.data(0) <= gt_rxbyterealign;
- addrmap_w.GT.RXCOMMADET.data(0) <= gt_rxcommadet;
+ cdc_status_array_bpm(0) <= sfp_rx_los;
+ cdc_status_array_bpm(1) <= sfp_mod_abs;
+ cdc_status_array_bpm(2) <= gt_powergood;
+ cdc_status_array_bpm(3) <= qpll_lock;
+ cdc_status_array_bpm(4) <= gt_rxcdrlock;
+ cdc_status_array_bpm(5) <= gt_rxresetdone;
+ cdc_status_array_bpm(6) <= gt_rxbyteisaligned;
+ cdc_status_array_bpm(7) <= gt_rxbyterealign;
+ cdc_status_array_bpm(8) <= gt_rxcommadet;
+ cdc_status_array_bpm(9) <= frame_error;
+ cdc_status_array_bpm(10) <= cnt_seq_mismatch;
+ cdc_status_array_bpm(11) <= seq_discontinuity;
+
+ cdc_status_array_bpm(43 downto 12) <= frame_valid_cnt;
+ cdc_status_array_bpm(75 downto 44) <= frame_invalid_cnt;
+ cdc_status_array_bpm(107 downto 76) <= frame_valid_rate;
+ cdc_status_array_bpm(139 downto 108) <= frame_invalid_rate;
+ cdc_status_array_bpm(155 downto 140) <= frame_seq_cnt;
+
+ inst_xpm_cdc_status_array_single: xpm_cdc_array_single
+ generic map (
+ DEST_SYNC_FF => 4,
+ INIT_SYNC_FF => 0,
+ SIM_ASSERT_CHK => 0,
+ SRC_INPUT_REG => 1,
+ WIDTH => cdc_status_array_axi'length
+ )
+ port map (
+ dest_out => cdc_status_array_axi,
+ dest_clk => s_axi_aclk,
+ src_clk => usrclk,
+ src_in => cdc_status_array_bpm
+ );
- addrmap_w.PROTOCOL.FRAMEERROR.data(0) <= frame_error;
- addrmap_w.PROTOCOL.SEQFRAMECNTERROR.data(0) <= cnt_seq_mismatch;
- addrmap_w.PROTOCOL.SEQFRAMEDISCONT.data(0) <= seq_discontinuity;
+ inst_xpm_cdc_control_array_single: xpm_cdc_array_single
+ generic map (
+ DEST_SYNC_FF => 4,
+ INIT_SYNC_FF => 0,
+ SIM_ASSERT_CHK => 0,
+ SRC_INPUT_REG => 1,
+ WIDTH => cdc_control_array_axi'length
+ )
+ port map (
+ dest_out => cdc_control_array_bpm,
+ dest_clk => usrclk,
+ src_clk => s_axi_aclk,
+ src_in => cdc_control_array_axi
+ );
- addrmap_w.VALIDFRAMECNT.data.data <= frame_valid_cnt;
- addrmap_w.INVALIDFRAMECNT.data.data <= frame_invalid_cnt;
- addrmap_w.VALIDFRAMERATE.data.data <= frame_valid_rate;
- addrmap_w.INVALIDFRAMERATE.data.data <= frame_invalid_rate;
- addrmap_w.FRAMESEQ.data.data <= frame_seq_cnt;
+ addrmap_w.SFP.RXLOS.data(0) <= cdc_status_array_axi(0);
+ addrmap_w.SFP.MODABS.data(0) <= cdc_status_array_axi(1);
+ addrmap_w.GT.POWERGOOD.data(0) <= cdc_status_array_axi(2);
+ addrmap_w.GT.QPLLLOCK.data(0) <= cdc_status_array_axi(3);
+ addrmap_w.GT.RXCDRLOCK.data(0) <= cdc_status_array_axi(4);
+ addrmap_w.GT.RXRESETDONE.data(0) <= cdc_status_array_axi(5);
+ addrmap_w.GT.RXBYTEISALIGNED.data(0) <= cdc_status_array_axi(6);
+ addrmap_w.GT.RXBYTEREALIGN.data(0) <= cdc_status_array_axi(7);
+ addrmap_w.GT.RXCOMMADET.data(0) <= cdc_status_array_axi(8);
+ addrmap_w.PROTOCOL.FRAMEERROR.data(0) <= cdc_status_array_axi(9);
+ addrmap_w.PROTOCOL.SEQFRAMECNTERROR.data(0) <= cdc_status_array_axi(10);
+ addrmap_w.PROTOCOL.SEQFRAMEDISCONT.data(0) <= cdc_status_array_axi(11);
+
+ addrmap_w.VALIDFRAMECNT.data.data <= cdc_status_array_axi(43 downto 12);
+ addrmap_w.INVALIDFRAMECNT.data.data <= cdc_status_array_axi(75 downto 44);
+ addrmap_w.VALIDFRAMERATE.data.data <= cdc_status_array_axi(107 downto 76);
+ addrmap_w.INVALIDFRAMERATE.data.data <= cdc_status_array_axi(139 downto 108);
+ addrmap_w.FRAMESEQ.data.data <= cdc_status_array_axi(155 downto 140);
+
+ cdc_control_array_axi(0) <= addrmap_r.GT.RXRSTDATAPATH.data(0);
+ cdc_control_array_axi(1) <= addrmap_r.GT.RXRSTPLLDATAPATH.data(0);
+ cdc_control_array_axi(2) <= addrmap_r.GT.RXCOMMADETEN.data(0);
end block blk_desyrdl;
@@ -274,10 +274,10 @@ begin
qpll1refclk_in(0) => qpll_ref_clk,
-- Control
- gtwiz_reset_rx_datapath_in => addrmap_r.GT.RXRSTDATAPATH.data,
- gtwiz_reset_rx_pll_and_datapath_in => addrmap_r.GT.RXRSTPLLDATAPATH.data,
+ gtwiz_reset_rx_datapath_in(0) => cdc_control_array_bpm(0),
+ gtwiz_reset_rx_pll_and_datapath_in(0) => cdc_control_array_bpm(1),
rxbufreset_in => "0",
- rxcommadeten_in => addrmap_r.GT.RXCOMMADETEN.data,
+ rxcommadeten_in(0) => cdc_control_array_bpm(2),
rx8b10ben_in => "1",
rxmcommaalignen_in => "1",
rxpcommaalignen_in => "1",
diff --git a/tcl/main.tcl b/tcl/main.tcl
index 8cf237e7fe02f4314a9d47831dafa0df551895db..92b13bb2359c108f15702db2f46a6becb4ffc3a1 100644
--- a/tcl/main.tcl
+++ b/tcl/main.tcl
@@ -19,6 +19,7 @@ proc setSources {} {
genModVerFile VHDL ../hdl/pkg_combpm_version.vhd
lappend Vhdl ../hdl/pkg_combpm_version.vhd
+ lappend Vhdl ../hdl/pkg_combpm.vhd
lappend Vhdl ../hdl/combpm_protocol_electron.vhd
lappend Vhdl ../hdl/top_combpm_electron.vhd
lappend Vhdl ../hdl/pkg_bpmpacket_stream.vhd