From e1e5dbbb7a53a697bddba9cbcad9da45ce302622 Mon Sep 17 00:00:00 2001
From: Romain Broucquart <romain.broucquart@synchrotron-soleil.fr>
Date: Tue, 1 Mar 2022 16:37:14 +0100
Subject: [PATCH] Top level corrections
* Connect true QPLL lock bit
* Attribute on QPLL_reset is now active high
---
hdl/top_combpm_electron.vhd | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hdl/top_combpm_electron.vhd b/hdl/top_combpm_electron.vhd
index 005a3df..18302d7 100644
--- a/hdl/top_combpm_electron.vhd
+++ b/hdl/top_combpm_electron.vhd
@@ -78,6 +78,9 @@ architecture struct of top_combpm_electron is
ATTRIBUTE X_INTERFACE_INFO of rst_n : SIGNAL is "xilinx.com:signal:reset:1.0 rst_n RST";
ATTRIBUTE X_INTERFACE_PARAMETER of rst_n : SIGNAL is "POLARITY ACTIVE_LOW";
+ ATTRIBUTE X_INTERFACE_INFO of qpll_reset : SIGNAL is "xilinx.com:signal:reset:1.0 qpll_reset RST";
+ ATTRIBUTE X_INTERFACE_PARAMETER of qpll_reset : SIGNAL is "POLARITY ACTIVE_HIGH";
+
ATTRIBUTE X_INTERFACE_PARAMETER of free_100_clk: SIGNAL is "FREQ_HZ 100000000";
ATTRIBUTE X_INTERFACE_PARAMETER of clk: SIGNAL is "FREQ_HZ 156250000, ASSOCIATED_BUSIF m_axis:s_axi";
@@ -161,7 +164,6 @@ architecture struct of top_combpm_electron is
signal gt_datarx : std_logic_vector(15 downto 0);
signal gt_powergood : std_logic;
- signal gt_qplllock : std_logic;
signal gt_rxclkactive : std_logic;
signal gt_rxcdrlock : std_logic;
signal gt_rxresetdone : std_logic;
@@ -202,7 +204,7 @@ begin
sfp_rxlos_i => sfp_rx_los,
sfp_modabs_i => sfp_mod_abs,
gt_powergood_i => gt_powergood,
- gt_qplllock_i => gt_qplllock,
+ gt_qplllock_i => qpll_lock,
gt_rxclkactive_i => gt_rxclkactive,
gt_rxcdrlock_i => gt_rxcdrlock,
gt_rxresetdone_i => gt_rxresetdone,
--
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