From 9662d8e22b7ee5975e0227ed6b62141887713a8d Mon Sep 17 00:00:00 2001
From: Romain Broucquart <romain.broucquart@synchrotron-soleil.fr>
Date: Fri, 24 Sep 2021 17:14:18 +0200
Subject: [PATCH] Wrap in a top level
* Wrap the protocol bloc and the aximm control in a structural top
level.
* Get rid of the CDC, use only one clock. Domain crossing will be
outside this bloc.
---
hdl/combpm_protocol_electron.vhd | 159 ++++-------------------
hdl/top_combpm_electron.vhd | 212 +++++++++++++++++++++++++++++++
2 files changed, 234 insertions(+), 137 deletions(-)
create mode 100644 hdl/top_combpm_electron.vhd
diff --git a/hdl/combpm_protocol_electron.vhd b/hdl/combpm_protocol_electron.vhd
index 6f893f2..52a18b2 100644
--- a/hdl/combpm_protocol_electron.vhd
+++ b/hdl/combpm_protocol_electron.vhd
@@ -9,9 +9,9 @@ use xpm.vcomponents.all;
entity combpm_protocol_electron is
port(
rst_n : in std_logic;
+ clk : in std_logic;
-- GT interface
- gt_clk : in std_logic;
gt_datarx : in std_logic_vector(15 downto 0);
gt_datatx : out std_logic_vector(15 downto 0);
gt_powergood : in std_logic;
@@ -32,7 +32,6 @@ entity combpm_protocol_electron is
gt_txdisable : out std_logic;
-- AXIS interface
- m_axi_aclk : in std_logic;
m_axi_tid : out std_logic_vector(0 downto 0);
m_axi_tdest : out std_logic_vector(9 downto 0);
m_axi_tdata : out std_logic_vector(127 downto 0);
@@ -43,29 +42,12 @@ entity combpm_protocol_electron is
m_axi_tvalid : out std_logic;
m_axi_tready : in std_logic;
- -- AXI bus interface
- S_AXI_CLK : in std_logic;
- S_AXI_RESETN : in std_logic;
- S_AXI_AWADDR : in std_logic_vector(7 downto 0);
- S_AXI_AWPROT : in std_logic_vector(2 downto 0);
- S_AXI_AWVALID : in std_logic;
- S_AXI_AWREADY : out std_logic;
- S_AXI_WDATA : in std_logic_vector(32-1 downto 0);
- S_AXI_WSTRB : in std_logic_vector(32/8-1 downto 0);
- S_AXI_WVALID : in std_logic;
- S_AXI_WREADY : out std_logic;
- S_AXI_BRESP : out std_logic_vector(1 downto 0);
- S_AXI_BVALID : out std_logic;
- S_AXI_BREADY : in std_logic;
- S_AXI_ARADDR : in std_logic_vector(7 downto 0);
- S_AXI_ARPROT : in std_logic_vector(2 downto 0);
- S_AXI_ARVALID : in std_logic;
- S_AXI_ARREADY : out std_logic;
- S_AXI_RDATA : out std_logic_vector(32-1 downto 0);
- S_AXI_RRESP : out std_logic_vector(1 downto 0);
- S_AXI_RVALID : out std_logic;
- S_AXI_RREADY : in std_logic
-
+ -- Status and control interface
+ tx_disable_i : in std_logic;
+ rx_commadeten_i : in std_logic;
+ srst_gt_i : in std_logic;
+ frame_counter_o : out std_logic_vector(15 downto 0);
+ frame_error_o : out std_logic
);
end entity combpm_protocol_electron;
@@ -102,9 +84,6 @@ architecture rtl of combpm_protocol_electron is
ATTRIBUTE X_INTERFACE_INFO of gt_txfault : SIGNAL is "soleil:user:gtsfp:1.0 GT txfault";
ATTRIBUTE X_INTERFACE_INFO of gt_rxlos : SIGNAL is "soleil:user:gtsfp:1.0 GT rxlos";
ATTRIBUTE X_INTERFACE_INFO of gt_modabs : SIGNAL is "soleil:user:gtsfp:1.0 GT modabs";
- ATTRIBUTE X_INTERFACE_INFO of gt_rstall : SIGNAL is "soleil:user:gtsfp:1.0 GT rstall";
- ATTRIBUTE X_INTERFACE_INFO of gt_rxcommadeten : SIGNAL is "soleil:user:gtsfp:1.0 GT rxcommadeten";
- ATTRIBUTE X_INTERFACE_INFO of gt_txdisable : SIGNAL is "soleil:user:gtsfp:1.0 GT txdisable";
ATTRIBUTE X_INTERFACE_INFO of rst_n : SIGNAL is "xilinx.com:signal:reset:1.0 rst_n RST";
ATTRIBUTE X_INTERFACE_PARAMETER of rst_n : SIGNAL is "POLARITY ACTIVE_LOW";
@@ -151,23 +130,8 @@ architecture rtl of combpm_protocol_electron is
signal frame_counter : unsigned(15 downto 0);
signal gt_rxcommadeten_s : std_logic;
- signal gt_rstall_s : std_logic;
-
- signal gt_txclkactive_cdc : std_logic;
- signal gt_rxclkactive_cdc : std_logic;
- signal gt_rxcdrlock_cdc : std_logic;
- signal gt_txresetdone_cdc : std_logic;
- signal gt_rxresetdone_cdc : std_logic;
- signal gt_rxbyteisaligned_cdc : std_logic;
- signal gt_rxbyterealign_cdc : std_logic;
- signal gt_rxcommadeten_cdc : std_logic;
- signal gt_rxcommadet_cdc : std_logic;
- signal frame_counter_cdc : std_logic_vector(15 downto 0);
- signal frame_error_cdc : std_logic;
- signal gt_rstall_cdc : std_logic;
signal itf_ready : std_logic;
- signal frame_error : std_logic;
begin
@@ -175,11 +139,11 @@ begin
---------------------
-- PACKET REGISTER --
---------------------
- p_packetreg:process(gt_clk, rst_n)
+ p_packetreg:process(clk, rst_n)
begin
if rst_n = '0' then
packet_reg <= (others => '0');
- elsif rising_edge(gt_clk) then
+ elsif rising_edge(clk) then
-- Simple shift register, 16 bits width, 14 word long
for I in 2 to 14 loop
packet_reg(I*16-1 downto (I-1)*16) <= packet_reg((I-1)*16-1 downto (I-2)*16);
@@ -253,12 +217,12 @@ begin
crc_result(31 downto 24) <= xorinv_crc_reg(7 downto 0);
-- Register
- p_crc:process(gt_clk, rst_n)
+ p_crc:process(clk, rst_n)
begin
if rst_n = '0' then
crc_reg <= C_CRCINIT;
crc_cnt <= (others => '0');
- elsif rising_edge(gt_clk) then
+ elsif rising_edge(clk) then
if crc_cnt = 0 then
if flag_sop_inc = '1' then
crc_cnt <= crc_cnt+1;
@@ -324,14 +288,14 @@ begin
m_axi_tuser <= "0";
m_axi_tlast <= '1'; -- One transfer is One packet.
- p_axis:process(m_axi_aclk, rst_n)
+ p_axis:process(clk, rst_n)
begin
if rst_n = '0' then
m_axi_tdata <= (others => '0');
m_axi_tvalid <= '0';
m_axi_tdest <= (others => '0');
- elsif rising_edge(m_axi_aclk) then
+ elsif rising_edge(clk) then
if flag_all = '1' then
-- Make AXIS packet
@@ -358,55 +322,20 @@ begin
end if;
end process p_axis;
- ---------------------------
- -- CLOCK DOMAIN CROSSING --
- ---------------------------
-
- cdc_gt_txclkactive_inst : xpm_cdc_single
- port map (src_clk=>gt_clk, dest_clk=>s_axi_clk, src_in=>gt_txclkactive, dest_out=>gt_txclkactive_cdc);
- cdc_gt_rxclkactive_inst : xpm_cdc_single
- port map (src_clk=>gt_clk, dest_clk=>s_axi_clk, src_in=>gt_rxclkactive, dest_out=>gt_rxclkactive_cdc);
- cdc_gt_rxcdrlock_inst : xpm_cdc_single
- port map (src_clk=>gt_clk, dest_clk=>s_axi_clk, src_in=>gt_rxcdrlock, dest_out=>gt_rxcdrlock_cdc);
- cdc_gt_txresetdone_inst : xpm_cdc_single
- port map (src_clk=>gt_clk, dest_clk=>s_axi_clk, src_in=>gt_txresetdone, dest_out=>gt_txresetdone_cdc);
- cdc_gt_rxresetdone_inst : xpm_cdc_single
- port map (src_clk=>gt_clk, dest_clk=>s_axi_clk, src_in=>gt_rxresetdone, dest_out=>gt_rxresetdone_cdc);
- cdc_gt_rxbyteisaligned_inst : xpm_cdc_single
- port map (src_clk=>gt_clk, dest_clk=>s_axi_clk, src_in=>gt_rxbyteisaligned, dest_out=>gt_rxbyteisaligned_cdc);
- cdc_gt_rxbyterealign_inst : xpm_cdc_single
- port map (src_clk=>gt_clk, dest_clk=>s_axi_clk, src_in=>gt_rxbyterealign, dest_out=>gt_rxbyterealign_cdc);
- cdc_frame_error_inst : xpm_cdc_single
- port map (src_clk=>gt_clk, dest_clk=>s_axi_clk, src_in=>frame_error, dest_out=>frame_error_cdc);
- cdc_gt_rxcommadet_inst : xpm_cdc_single
- port map (src_clk=>gt_clk, dest_clk=>s_axi_clk, src_in=>gt_rxcommadet, dest_out=>gt_rxcommadet_cdc);
-
- cdc_gt_frame_counter_cdc : xpm_cdc_gray
- generic map ( WIDTH=>16)
- port map (src_clk=>gt_clk, dest_clk=>s_axi_clk, src_in_bin=>std_logic_vector(frame_counter), dest_out_bin=>frame_counter_cdc);
-
- cdc_gt_rstall_inst : xpm_cdc_single
- port map (src_clk=>s_axi_clk, dest_clk=>gt_clk, src_in=>gt_rstall_s, dest_out=>gt_rstall_cdc);
- cdc_gt_rxcommadeten_inst : xpm_cdc_single
- port map (src_clk=>s_axi_clk, dest_clk=>gt_clk, src_in=>gt_rxcommadeten_s, dest_out=>gt_rxcommadeten_cdc);
-
------------------------
-- CONTROL AND STATUS --
------------------------
- frame_error <= flag_any xor flag_all;
- gt_rxcommadeten <= gt_rxcommadeten_cdc;
+ frame_error_o <= flag_any xor flag_all;
+ frame_counter_o <= std_logic_vector(frame_counter);
itf_ready <= gt_txresetdone and gt_rxresetdone and gt_powergood and gt_qplllock
- and gt_rxbyteisaligned and (not gt_rstall_cdc);
-
- -- reset
- gt_rstall <= gt_rstall_cdc;
+ and gt_rxbyteisaligned and (not srst_gt_i);
-- frame counter
- p_framecnt:process(gt_clk, rst_n)
+ p_framecnt:process(clk, rst_n)
begin
if rst_n = '0' then
frame_counter <= (others => '0');
- elsif rising_edge(gt_clk) then
+ elsif rising_edge(clk) then
if flag_all = '1' then
frame_counter <= frame_counter+1;
end if;
@@ -414,54 +343,10 @@ begin
end process p_framecnt;
- S_AXI_RESET <= not S_AXI_RESETN;
- axiitf_inst: entity work.combpm_protocol_electron_ctrl_axi
- generic map(
- G_ADDR_W => 8
- )
- port map(
- sfp_txfault_i => gt_txfault,
- sfp_rxlos_i => gt_rxlos,
- sfp_modabs_i => gt_modabs,
- sfp_txdisable_o => gt_txdisable,
- gt_powergood_i => gt_powergood,
- gt_qplllock_i => gt_qplllock,
- gt_txclkactive_i => gt_txclkactive_cdc,
- gt_rxclkactive_i => gt_rxclkactive_cdc,
- gt_rxcdrlock_i => gt_rxcdrlock_cdc,
- gt_txresetdone_i => gt_txresetdone_cdc,
- gt_rxresetdone_i => gt_rxresetdone_cdc,
- gt_rxbyteisaligned_i => gt_rxbyteisaligned_cdc,
- gt_rxbyterealign_i => gt_rxbyterealign_cdc,
- gt_rxcommadet_i => gt_rxcommadet_cdc,
- gt_rxcommadeten_o => gt_rxcommadeten_s,
- gt_rstall_o => gt_rstall_s,
- protocol_framecnt_i => frame_counter_cdc,
- protocol_frameerror_i => frame_error_cdc,
-
- clk => S_AXI_CLK,
- reset => S_AXI_RESET,
- S_AXI_AWADDR => S_AXI_AWADDR,
- S_AXI_AWPROT => S_AXI_AWPROT,
- S_AXI_AWVALID => S_AXI_AWVALID,
- S_AXI_AWREADY => S_AXI_AWREADY,
- S_AXI_WDATA => S_AXI_WDATA,
- S_AXI_WSTRB => S_AXI_WSTRB,
- S_AXI_WVALID => S_AXI_WVALID,
- S_AXI_WREADY => S_AXI_WREADY,
- S_AXI_BRESP => S_AXI_BRESP,
- S_AXI_BVALID => S_AXI_BVALID,
- S_AXI_BREADY => S_AXI_BREADY,
- S_AXI_ARADDR => S_AXI_ARADDR,
- S_AXI_ARPROT => S_AXI_ARPROT,
- S_AXI_ARVALID => S_AXI_ARVALID,
- S_AXI_ARREADY => S_AXI_ARREADY,
- S_AXI_RDATA => S_AXI_RDATA,
- S_AXI_RRESP => S_AXI_RRESP,
- S_AXI_RVALID => S_AXI_RVALID,
- S_AXI_RREADY => S_AXI_RREADY
-
- );
+ -- Direct connexion to GT/SFP
+ gt_txdisable <= tx_disable_i;
+ gt_rstall <= srst_gt_i;
+ gt_rxcommadeten <= rx_commadeten_i;
end architecture rtl;
diff --git a/hdl/top_combpm_electron.vhd b/hdl/top_combpm_electron.vhd
new file mode 100644
index 0000000..7348f4e
--- /dev/null
+++ b/hdl/top_combpm_electron.vhd
@@ -0,0 +1,212 @@
+-- PROJECT FOFB
+-- COMBPM ELECTRON TOP LEVEL
+-- RBR
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity top_combpm_electron is
+ port(
+ clk : in std_logic;
+ rst_n : in std_logic;
+
+ -- GT interface
+ gt_datarx : in std_logic_vector(15 downto 0);
+ gt_datatx : out std_logic_vector(15 downto 0);
+ gt_powergood : in std_logic;
+ gt_qplllock : in std_logic;
+ gt_txclkactive : in std_logic;
+ gt_rxclkactive : in std_logic;
+ gt_txresetdone : in std_logic;
+ gt_rxresetdone : in std_logic;
+ gt_rxcdrlock : in std_logic;
+ gt_rxbyteisaligned : in std_logic;
+ gt_rxbyterealign : in std_logic;
+ gt_rxcommadet : in std_logic;
+ gt_txfault : in std_logic;
+ gt_rxlos : in std_logic;
+ gt_modabs : in std_logic;
+ gt_rstall : out std_logic;
+ gt_rxcommadeten : out std_logic;
+ gt_txdisable : out std_logic;
+
+ -- AXIS interface
+ m_axi_tid : out std_logic_vector(0 downto 0);
+ m_axi_tdest : out std_logic_vector(9 downto 0);
+ m_axi_tdata : out std_logic_vector(127 downto 0);
+ m_axi_tstrb : out std_logic_vector(15 downto 0);
+ m_axi_tkeep : out std_logic_vector(15 downto 0);
+ m_axi_tlast : out std_logic;
+ m_axi_tuser : out std_logic_vector(0 downto 0);
+ m_axi_tvalid : out std_logic;
+ m_axi_tready : in std_logic;
+
+ -- AXI bus interface
+ S_AXI_AWADDR : in std_logic_vector(7 downto 0);
+ S_AXI_AWPROT : in std_logic_vector(2 downto 0);
+ S_AXI_AWVALID : in std_logic;
+ S_AXI_AWREADY : out std_logic;
+ S_AXI_WDATA : in std_logic_vector(32-1 downto 0);
+ S_AXI_WSTRB : in std_logic_vector(32/8-1 downto 0);
+ S_AXI_WVALID : in std_logic;
+ S_AXI_WREADY : out std_logic;
+ S_AXI_BRESP : out std_logic_vector(1 downto 0);
+ S_AXI_BVALID : out std_logic;
+ S_AXI_BREADY : in std_logic;
+ S_AXI_ARADDR : in std_logic_vector(7 downto 0);
+ S_AXI_ARPROT : in std_logic_vector(2 downto 0);
+ S_AXI_ARVALID : in std_logic;
+ S_AXI_ARREADY : out std_logic;
+ S_AXI_RDATA : out std_logic_vector(32-1 downto 0);
+ S_AXI_RRESP : out std_logic_vector(1 downto 0);
+ S_AXI_RVALID : out std_logic;
+ S_AXI_RREADY : in std_logic
+ );
+end top_combpm_electron;
+
+architecture struct of top_combpm_electron is
+
+ --------------------------
+ -- INTERFACE ATTRIBUTES --
+ --------------------------
+ ATTRIBUTE X_INTERFACE_INFO : STRING;
+ ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
+
+ ATTRIBUTE X_INTERFACE_INFO of m_axi_tid : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TID";
+ ATTRIBUTE X_INTERFACE_INFO of m_axi_tdest : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TDEST";
+ ATTRIBUTE X_INTERFACE_INFO of m_axi_tdata : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TDATA";
+ ATTRIBUTE X_INTERFACE_INFO of m_axi_tstrb : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TSTRB";
+ ATTRIBUTE X_INTERFACE_INFO of m_axi_tkeep : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TKEEP";
+ ATTRIBUTE X_INTERFACE_INFO of m_axi_tlast : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TLAST";
+ ATTRIBUTE X_INTERFACE_INFO of m_axi_tuser : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TUSER";
+ ATTRIBUTE X_INTERFACE_INFO of m_axi_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TVALID";
+ ATTRIBUTE X_INTERFACE_INFO of m_axi_tready : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TREADY";
+
+ ATTRIBUTE X_INTERFACE_INFO of gt_datarx : SIGNAL is "soleil:user:gtsfp:1.0 GT datarx";
+ ATTRIBUTE X_INTERFACE_INFO of gt_datatx : SIGNAL is "soleil:user:gtsfp:1.0 GT datatx";
+ ATTRIBUTE X_INTERFACE_INFO of gt_powergood : SIGNAL is "soleil:user:gtsfp:1.0 GT powergood";
+ ATTRIBUTE X_INTERFACE_INFO of gt_qplllock : SIGNAL is "soleil:user:gtsfp:1.0 GT qplllock";
+ ATTRIBUTE X_INTERFACE_INFO of gt_txclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT txclkactive";
+ ATTRIBUTE X_INTERFACE_INFO of gt_rxclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT rxclkactive";
+ ATTRIBUTE X_INTERFACE_INFO of gt_txresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT txresetdone";
+ ATTRIBUTE X_INTERFACE_INFO of gt_rxresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT rxresetdone";
+ ATTRIBUTE X_INTERFACE_INFO of gt_rxcdrlock : SIGNAL is "soleil:user:gtsfp:1.0 GT rxcdrlock";
+ ATTRIBUTE X_INTERFACE_INFO of gt_rxbyteisaligned : SIGNAL is "soleil:user:gtsfp:1.0 GT rxbyteisaligned";
+ ATTRIBUTE X_INTERFACE_INFO of gt_rxbyterealign : SIGNAL is "soleil:user:gtsfp:1.0 GT rxbyterealign";
+ ATTRIBUTE X_INTERFACE_INFO of gt_rxcommadet : SIGNAL is "soleil:user:gtsfp:1.0 GT rxcommadet";
+ ATTRIBUTE X_INTERFACE_INFO of gt_txfault : SIGNAL is "soleil:user:gtsfp:1.0 GT txfault";
+ ATTRIBUTE X_INTERFACE_INFO of gt_rxlos : SIGNAL is "soleil:user:gtsfp:1.0 GT rxlos";
+ ATTRIBUTE X_INTERFACE_INFO of gt_modabs : SIGNAL is "soleil:user:gtsfp:1.0 GT modabs";
+ ATTRIBUTE X_INTERFACE_INFO of gt_rstall : SIGNAL is "soleil:user:gtsfp:1.0 GT rstall";
+ ATTRIBUTE X_INTERFACE_INFO of gt_rxcommadeten : SIGNAL is "soleil:user:gtsfp:1.0 GT rxcommadeten";
+ ATTRIBUTE X_INTERFACE_INFO of gt_txdisable : SIGNAL is "soleil:user:gtsfp:1.0 GT txdisable";
+
+ ATTRIBUTE X_INTERFACE_INFO of rst_n : SIGNAL is "xilinx.com:signal:reset:1.0 rst_n RST";
+ ATTRIBUTE X_INTERFACE_PARAMETER of rst_n : SIGNAL is "POLARITY ACTIVE_LOW";
+
+ ------------------------
+ -- SIGNAL DECLARATION --
+ ------------------------
+ signal rst : std_logic;
+ signal tx_disable : std_logic;
+ signal rx_commadeten : std_logic;
+ signal srst_gt : std_logic;
+ signal frame_counter : std_logic_vector(15 downto 0);
+ signal frame_error : std_logic;
+
+begin
+
+ -- Reset invert polarity
+ rst <= not rst_n;
+
+ axiitf_inst: entity work.combpm_protocol_electron_ctrl_axi
+ generic map(
+ G_ADDR_W => 8
+ )
+ port map(
+ sfp_txfault_i => gt_txfault,
+ sfp_rxlos_i => gt_rxlos,
+ sfp_modabs_i => gt_modabs,
+ sfp_txdisable_o => tx_disable,
+ gt_powergood_i => gt_powergood,
+ gt_qplllock_i => gt_qplllock,
+ gt_txclkactive_i => gt_txclkactive,
+ gt_rxclkactive_i => gt_rxclkactive,
+ gt_rxcdrlock_i => gt_rxcdrlock,
+ gt_txresetdone_i => gt_txresetdone,
+ gt_rxresetdone_i => gt_rxresetdone,
+ gt_rxbyteisaligned_i => gt_rxbyteisaligned,
+ gt_rxbyterealign_i => gt_rxbyterealign,
+ gt_rxcommadet_i => gt_rxcommadet,
+ gt_rxcommadeten_o => rx_commadeten,
+ gt_rstall_o => srst_gt,
+ protocol_framecnt_i => frame_counter,
+ protocol_frameerror_i => frame_error,
+
+ clk => clk,
+ reset => rst,
+ S_AXI_AWADDR => S_AXI_AWADDR,
+ S_AXI_AWPROT => S_AXI_AWPROT,
+ S_AXI_AWVALID => S_AXI_AWVALID,
+ S_AXI_AWREADY => S_AXI_AWREADY,
+ S_AXI_WDATA => S_AXI_WDATA,
+ S_AXI_WSTRB => S_AXI_WSTRB,
+ S_AXI_WVALID => S_AXI_WVALID,
+ S_AXI_WREADY => S_AXI_WREADY,
+ S_AXI_BRESP => S_AXI_BRESP,
+ S_AXI_BVALID => S_AXI_BVALID,
+ S_AXI_BREADY => S_AXI_BREADY,
+ S_AXI_ARADDR => S_AXI_ARADDR,
+ S_AXI_ARPROT => S_AXI_ARPROT,
+ S_AXI_ARVALID => S_AXI_ARVALID,
+ S_AXI_ARREADY => S_AXI_ARREADY,
+ S_AXI_RDATA => S_AXI_RDATA,
+ S_AXI_RRESP => S_AXI_RRESP,
+ S_AXI_RVALID => S_AXI_RVALID,
+ S_AXI_RREADY => S_AXI_RREADY
+ );
+
+ protocol_inst: entity work.combpm_protocol_electron
+ port map(
+ rst_n => rst_n,
+ clk => clk,
+ gt_datarx => gt_datarx,
+ gt_datatx => gt_datatx,
+ gt_powergood => gt_powergood,
+ gt_qplllock => gt_qplllock,
+ gt_txclkactive => gt_txclkactive,
+ gt_rxclkactive => gt_rxclkactive,
+ gt_txresetdone => gt_txresetdone,
+ gt_rxresetdone => gt_rxresetdone,
+ gt_rxcdrlock => gt_rxcdrlock,
+ gt_rxbyteisaligned => gt_rxbyteisaligned,
+ gt_rxbyterealign => gt_rxbyterealign,
+ gt_rxcommadet => gt_rxcommadet,
+ gt_txfault => gt_txfault,
+ gt_rxlos => gt_rxlos,
+ gt_modabs => gt_modabs,
+ gt_rstall => gt_rstall,
+ gt_rxcommadeten => gt_rxcommadeten,
+ gt_txdisable => gt_txdisable,
+
+ m_axi_tid => m_axi_tid,
+ m_axi_tdest => m_axi_tdest,
+ m_axi_tdata => m_axi_tdata,
+ m_axi_tstrb => m_axi_tstrb,
+ m_axi_tkeep => m_axi_tkeep,
+ m_axi_tlast => m_axi_tlast,
+ m_axi_tuser => m_axi_tuser,
+ m_axi_tvalid => m_axi_tvalid,
+ m_axi_tready => m_axi_tready,
+
+ tx_disable_i => tx_disable,
+ rx_commadeten_i => rx_commadeten,
+ srst_gt_i => srst_gt,
+ frame_counter_o => frame_counter,
+ frame_error_o => frame_error
+
+ );
+
+
+end architecture struct;
--
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