From 934c2816d2ce7b0eaf27e6dfc3a874aa384e749a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Romain=20Bron=C3=A8s?= <romain.brones@synchrotron-soleil.fr>
Date: Thu, 10 Oct 2024 14:27:27 +0200
Subject: [PATCH] Add CDC between AXIMM and logic
* this is cleaner, but they were false path
* also fix the AXIMM reset
---
hdl/top_combpm_electron.vhd | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/hdl/top_combpm_electron.vhd b/hdl/top_combpm_electron.vhd
index 6089b09..abb76a1 100644
--- a/hdl/top_combpm_electron.vhd
+++ b/hdl/top_combpm_electron.vhd
@@ -67,7 +67,6 @@ architecture struct of top_combpm_electron is
-- SIGNAL DECLARATION --
------------------------
signal sync_resetn : std_logic; -- This is async reset with sync deassertion
- signal sync_reset : std_logic; -- This is async reset with sync deassertion
signal usrclk : std_logic;
signal rst : std_logic;
@@ -94,10 +93,10 @@ architecture struct of top_combpm_electron is
signal addrmap_w : t_addrmap_combpm_in;
signal addrmap_r : t_addrmap_combpm_out;
- signal cdc_status_array_axi : std_logic_vector(155 downto 0); -- CDC, clock axi side
- signal cdc_status_array_bpm : std_logic_vector(155 downto 0); -- CDC, clock bpm side
- signal cdc_control_array_axi : std_logic_vector(2 downto 0); -- CDC, clock axi side
- signal cdc_control_array_bpm : std_logic_vector(2 downto 0); -- CDC, clock bpm side
+ signal cdc_status_array_axi : std_logic_vector(156 downto 0); -- CDC, clock axi side
+ signal cdc_status_array_bpm : std_logic_vector(156 downto 0); -- CDC, clock bpm side
+ signal cdc_control_array_axi : std_logic_vector(3 downto 0); -- CDC, clock axi side
+ signal cdc_control_array_bpm : std_logic_vector(3 downto 0); -- CDC, clock bpm side
signal m_axis_decoded_tvalid : std_logic;
signal m_axis_decoded_tdata : std_logic_vector(2*C_W_POS+C_W_BPMID+C_W_SEQ-1 downto 0);
@@ -142,7 +141,6 @@ begin
-- Reset invert polarity
rst <= not rst_n;
- sync_reset <= not sync_resetn;
-- Debug
debug_datarx <= gt_datarx;
@@ -169,7 +167,7 @@ begin
inst_aximm: entity desyrdl.combpm
port map(
pi_clock => s_axi_aclk,
- pi_reset => sync_reset,
+ pi_reset => rst,
pi_s_top => s_axi_m2s,
po_s_top => s_axi_s2m,
pi_addrmap => addrmap_w,
@@ -245,10 +243,12 @@ begin
addrmap_w.VALIDFRAMERATE.data.data <= cdc_status_array_axi(107 downto 76);
addrmap_w.INVALIDFRAMERATE.data.data <= cdc_status_array_axi(139 downto 108);
addrmap_w.FRAMESEQ.data.data <= cdc_status_array_axi(155 downto 140);
+ addrmap_w.GT_STATUS.RXCLKACTIVE.data(0) <= cdc_status_array_axi(156);
cdc_control_array_axi(0) <= addrmap_r.GT_CONTROL.RXRSTDATAPATH.data(0);
cdc_control_array_axi(1) <= addrmap_r.GT_CONTROL.RXRSTPLLDATAPATH.data(0);
cdc_control_array_axi(2) <= addrmap_r.GT_CONTROL.RXCOMMADETEN.data(0);
+ cdc_control_array_axi(3) <= addrmap_r.RESET_ERROR.SOFTRESET.data(0);
end block blk_desyrdl;
@@ -270,7 +270,7 @@ begin
m_axis_tuser_mcts => open,
mc_time => mc_time,
- soft_reset => addrmap_r.RESET.SOFTRESET.data(0),
+ soft_reset => cdc_control_array_bpm(3),
seq_offset => signed(addrmap_r.SEQ_OFFSET.data.data),
frame_seq_cnt => frame_seq_cnt,
frame_valid_cnt => frame_valid_cnt,
@@ -280,7 +280,7 @@ begin
flag_cnt_seq_mismatch => cnt_seq_mismatch,
flag_seq_discontinuity => seq_discontinuity,
flag_frame_error => frame_error,
- flag_reset => addrmap_r.RESET_ERROR.SOFTRESET.data(0)
+ flag_reset => cdc_control_array_bpm(3)
);
-- Pack fo convenience
@@ -325,7 +325,7 @@ begin
-- Status
gtwiz_userclk_tx_active_out => open,
- gtwiz_userclk_rx_active_out => addrmap_w.GT_STATUS.RXCLKACTIVE.data,
+ gtwiz_userclk_rx_active_out(0) => cdc_status_array_bpm(156),
gtwiz_reset_tx_done_out => open,
gtwiz_reset_rx_done_out(0) => gt_rxresetdone,
gtpowergood_out(0) => gt_powergood,
--
GitLab