diff --git a/hdl/combpm_packet_filter.vhd b/hdl/combpm_packet_filter.vhd index b0f6220cf20f933d78d01c43a125b306be23bc79..b065bf689bd307892aa9b9dbc6c96e5f0d126fb7 100644 --- a/hdl/combpm_packet_filter.vhd +++ b/hdl/combpm_packet_filter.vhd @@ -2,14 +2,16 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -use work.pkg_bpmpacket_stream.all; library desy; use desy.ram_tdp; +use work.pkg_combpm.C_W_BPMID; + entity combpm_packet_filter is generic( - G_W_ADDR_TABLE : natural + G_W_ADDR_TABLE : natural; + G_W_TDATA : natural ); port( axis_clk : in std_logic; @@ -17,14 +19,14 @@ entity combpm_packet_filter is axis_rst_n : in std_logic; -- AXIS SLAVE INTERFACE - s_axis_tdest : in std_logic_vector(C_TDEST_W-1 downto 0); - s_axis_tdata : in std_logic_vector(C_TDATA_W-1 downto 0); s_axis_tvalid : in std_logic; + s_axis_tdata : in std_logic_vector(G_W_TDATA-1 downto 0); + s_axis_tuser_bpmid : in std_logic_vector(C_W_BPMID-1 downto 0); -- AXIS MASTER INTERFACE - m_axis_tdest : out std_logic_vector(C_TDEST_W-1 downto 0); - m_axis_tdata : out std_logic_vector(C_TDATA_W-1 downto 0); m_axis_tvalid : out std_logic; + m_axis_tdata : out std_logic_vector(G_W_TDATA-1 downto 0); + m_axis_tdest : out std_logic_vector(C_TDEST_W-1 downto 0); -- Table configuration interface pi_table_en : in std_logic; @@ -42,8 +44,9 @@ architecture rtl of combpm_packet_filter is ------------------------ -- SIGNAL DECLARATION -- ------------------------ - signal in_packet : t_bpmpacket; - signal out_packet : t_bpmpacket; + signal r1_tdata : std_logic_vector(G_W_TDATA-1 downto 0); + signal r2_tdata : std_logic_vector(G_W_TDATA-1 downto 0); + signal r_bpmid : std_logic_vector(C_W_BPMID-1 downto 0); signal table_data : std_logic_vector(7 downto 0); @@ -60,19 +63,22 @@ begin p_main: process(axis_clk, axis_rst_n) begin if axis_rst_n = '0' then - in_packet <= slv2bpmpacket(zero_packet); - out_packet <= slv2bpmpacket(zero_packet); + r1_tdata <= (others => '0'); + r2_tdata <= (others => '0'); + r_bpmid <= (others => '0'); + tvalid_r <= (others => '0'); elsif rising_edge(axis_clk) then -- Register input packet if s_axis_tvalid = '1' then - in_packet <= slv2bpmpacket(s_axis_tdata); + r1_tdata <= s_axis_tdata; + r_bpmid <= s_axis_tuser_bpmid; end if; tvalid_r(tvalid_r'left downto 1) <= tvalid_r(tvalid_r'left-1 downto 0); tvalid_r(0) <= s_axis_tvalid; - out_packet <= in_packet; + r2_tdata <= r1_tdata; end if; end process; @@ -80,9 +86,9 @@ begin ----------------- -- AXIS OUTPUT -- ----------------- - m_axis_tdest <= std_logic_vector(resize(unsigned(table_data(6 downto 0)), C_TDEST_W)); - m_axis_tdata <= bpmpacket2slv(out_packet); - m_axis_tvalid <= tvalid_r(tvalid_r'left) and table_data(7); + m_axis_tdest <= std_logic_vector(resize(unsigned(table_data(6 downto 0)), C_TDEST_W)); + m_axis_tdata <= r2_tdata; + m_axis_tvalid <= tvalid_r(tvalid_r'left) and table_data(7); ------------------ -- FILTER TABLE -- @@ -103,7 +109,7 @@ begin pi_clk_b => axis_clk, pi_en_b => '1', pi_we_b => '0', - pi_addr_b => in_packet.bpm_id(G_W_ADDR_TABLE-1 downto 0), + pi_addr_b => r_bpmid(G_W_ADDR_TABLE-1 downto 0), pi_data_b => (others => '0'), po_data_b => table_data ); diff --git a/hdl/combpm_protocol_electron.vhd b/hdl/combpm_protocol_electron.vhd index 4ac931938531325dbac6671e8ff421c1a98b4ee7..aab0390dc13062c9499ef23c324c671d859251cd 100644 --- a/hdl/combpm_protocol_electron.vhd +++ b/hdl/combpm_protocol_electron.vhd @@ -3,7 +3,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -use work.pkg_bpmpacket_stream.all; +use work.pkg_combpm.all; entity combpm_protocol_electron is port( @@ -17,7 +17,12 @@ entity combpm_protocol_electron is gt_datarx : in std_logic_vector(15 downto 0); -- Deserialized data. -- AXIS interface - m_axis_m2s : out t_bpmpacket_axis_m2s; + m_axis_tvalid : out std_logic; + m_axis_tdata_posx : out std_logic_vector(C_W_POS-1 downto 0); + m_axis_tdata_posy : out std_logic_vector(C_W_POS-1 downto 0); + m_axis_tdata_bpmid : out std_logic_vector(C_W_BPMID-1 downto 0); + m_axis_tdata_faseq : out std_logic_vector(C_W_SEQ-1 downto 0); + m_axis_tuser_mcts : out std_logic_vector(C_W_MCTS-1 downto 0); -- Status and control interface soft_reset : in std_logic; -- Reset all counters. @@ -82,8 +87,7 @@ architecture rtl of combpm_protocol_electron is signal rate_valid_r : unsigned(31 downto 0); signal rate_invalid_r : unsigned(31 downto 0); - signal packet : t_bpmpacket; - signal m_axi_tvalid : std_logic; + signal axis_tvalid : std_logic; signal cnt_seq_mismatch : std_logic; signal seq_discontinuity : std_logic; @@ -270,32 +274,30 @@ begin -------------- -- AXIS OUT -- -------------- - m_axis_m2s.tdest <= (others => '0'); - m_axis_m2s.tdata <= bpmpacket2slv(packet); - m_axis_m2s.tlast <= '1'; -- One transfer is One packet. - m_axis_m2s.tvalid <= m_axi_tvalid; - - p_axis:process(clk, rst_n) begin if rst_n = '0' then - packet <= C_BPMPACKET_ZERO; - m_axi_tvalid <= '0'; + m_axis_tvalid <= '0'; + m_axis_tdata_posx <= (others => '0'); + m_axis_tdata_posy <= (others => '0'); + m_axis_tdata_bpmid <= (others => '0'); + m_axis_tuser_mcts <= (others => '0'); + m_axis_tdata_faseq <= (others => '0'); elsif rising_edge(clk) then if flag_all = '1' then -- Make AXIS packet - packet.pos_x <= packet_xpos; - packet.pos_y <= packet_ypos; - packet.bpm_id <= "000000" & packet_bpmid; - packet.mc_timestamp <= mc_time; - packet.fa_seq <= packet_timestamp(7 downto 0); + m_axis_tdata_posx <= packet_xpos; + m_axis_tdata_posy <= packet_ypos; + m_axis_tdata_bpmid <= "000000" & packet_bpmid; + m_axis_tuser_mcts <= mc_time; + m_axis_tdata_faseq <= packet_timestamp; -- AXIS TVALID - m_axi_tvalid <= not soft_reset; + m_axis_tvalid <= not soft_reset; else - m_axi_tvalid <= '0'; + m_axis_tvalid <= '0'; end if; end if; end process p_axis; diff --git a/hdl/pkg_bpmpacket_stream.vhd b/hdl/pkg_bpmpacket_stream.vhd deleted file mode 100644 index 4bda9eaa6bc869aeefcc2d43447f2cbaf035c722..0000000000000000000000000000000000000000 --- a/hdl/pkg_bpmpacket_stream.vhd +++ /dev/null @@ -1,90 +0,0 @@ --- Package BPMPACKET STREAM --- this package describe the format of the AXI-Stream interface used by blocs of the module COMBPM. --- --- The usefull things are : --- * Two record types for port interfaces: t_bpmpacket_axis_m2s and t_bpmpacket_axis_s2m. --- * One record type for frame fields: t_bpmpacket. --- * Two functions to transform TDATA (std_logic_vector) to/from t_bpmpacket: slv2bpmpacket and bpmpacket2slv. -library ieee; -use ieee.std_logic_1164.all; - -package pkg_bpmpacket_stream is - - ---------------------- - -- MACRO PARAMETERS -- - ---------------------- - constant C_TDEST_W : natural := 7; - constant C_TDATA_W : natural := 128; - - --------------------------------- - -- AXIS MASTER/SLAVE INTERFACE -- - --------------------------------- - type t_bpmpacket_axis_m2s is record - tdest : std_logic_vector(C_TDEST_W-1 downto 0); - tdata : std_logic_vector(C_TDATA_W-1 downto 0); - tlast : std_logic; - tvalid : std_logic; - end record t_bpmpacket_axis_m2s; - - type t_bpmpacket_axis_s2m is record - tready : std_logic; - end record t_bpmpacket_axis_s2m; - - ------------------------ - -- AXIS STREAM PACKET -- - ------------------------ - type t_bpmpacket is record - pos_x : std_logic_vector(31 downto 0); - pos_y : std_logic_vector(31 downto 0); - bpm_id : std_logic_vector(15 downto 0); - mc_timestamp : std_logic_vector(39 downto 0); - fa_seq : std_logic_vector(7 downto 0); - end record t_bpmpacket; - - constant C_BPMPACKET_ZERO : t_bpmpacket := ( - pos_x => (others => '0'), - pos_y => (others => '0'), - bpm_id => (others => '0'), - mc_timestamp => (others => '0'), - fa_seq => (others => '0') - ); - - function slv2bpmpacket( - signal tdata : std_logic_vector(C_TDATA_W-1 downto 0) - ) - return t_bpmpacket; - - function bpmpacket2slv( - signal packet : t_bpmpacket - ) - return std_logic_vector; - - -end package; - -package body pkg_bpmpacket_stream is - - - function slv2bpmpacket( - signal tdata : std_logic_vector(C_TDATA_W-1 downto 0) - ) - return t_bpmpacket is - variable packet : t_bpmpacket; - begin - packet.pos_x := tdata(31 downto 0); - packet.pos_y := tdata(63 downto 32); - packet.bpm_id := tdata(79 downto 64); - packet.mc_timestamp := tdata(119 downto 80); - packet.fa_seq := tdata(127 downto 120); - return packet; - end function; - - function bpmpacket2slv( - signal packet : t_bpmpacket - ) - return std_logic_vector is - begin - return packet.fa_seq & packet.mc_timestamp & packet.bpm_id & packet.pos_y & packet.pos_x; - end function; - -end package body; diff --git a/hdl/pkg_combpm.vhd b/hdl/pkg_combpm.vhd index febec73a280eaf86f0747d1c211bc6ee023401de..336751b203ee6d767da3ed7e466da87372cb7e80 100644 --- a/hdl/pkg_combpm.vhd +++ b/hdl/pkg_combpm.vhd @@ -9,6 +9,11 @@ package pkg_combpm is constant C_W_ADDR_TABLE : natural := 8; + constant C_W_TDEST : natural := 7; + constant C_W_POS : natural := 32; + constant C_W_BPMID : natural := 16; + constant C_W_SEQ : natural := 16; + constant C_W_MCTS : natural := 40; ------------------------- -- GT WIZARD COMPONENT -- @@ -71,4 +76,4 @@ package pkg_combpm is ); END COMPONENT; -end package; \ No newline at end of file +end package; diff --git a/hdl/top_combpm_electron.vhd b/hdl/top_combpm_electron.vhd index f073ee4cbdbad1fc5da5eca299fbe7c5df849c62..f24bfaa527c92b84a0a5e54e9999a6e03999b7d8 100644 --- a/hdl/top_combpm_electron.vhd +++ b/hdl/top_combpm_electron.vhd @@ -13,7 +13,6 @@ library desyrdl; use desyrdl.common.all; use desyrdl.pkg_combpm.all; -use work.pkg_bpmpacket_stream.all; use work.pkg_combpm_version.all; use work.pkg_combpm.all; @@ -48,8 +47,11 @@ entity top_combpm_electron is -- AXIS interface m_axis_aclk : out std_logic; - m_axis_tdata : out std_logic_vector(C_TDATA_W-1 downto 0); - m_axis_tdest : out std_logic_vector(C_TDEST_W-1 downto 0); + m_axis_tdata_posx : out std_logic_vector(C_W_POS-1 downto 0); + m_axis_tdata_posy : out std_logic_vector(C_W_POS-1 downto 0); + m_axis_tdata_bpmid : out std_logic_vector(C_W_BPMID-1 downto 0); + m_axis_tdata_seq : out std_logic_vector(C_W_SEQ-1 downto 0); + m_axis_tdest : out std_logic_vector(C_W_TDEST-1 downto 0); m_axis_tvalid : out std_logic; -- AXI bus interface @@ -97,7 +99,14 @@ architecture struct of top_combpm_electron is signal cdc_control_array_axi : std_logic_vector(2 downto 0); -- CDC, clock axi side signal cdc_control_array_bpm : std_logic_vector(2 downto 0); -- CDC, clock bpm side - signal m_axis_decoded_m2s : t_bpmpacket_axis_m2s; + signal m_axis_decoded_tvalid : std_logic; + signal m_axis_decoded_tdata : std_logic_vector(2*C_W_POS+C_W_BPMID+C_W_SEQ-1 downto 0); + signal m_axis_decoded_tdata_posx : std_logic_vector(C_W_POS-1 downto 0); + signal m_axis_decoded_tdata_posy : std_logic_vector(C_W_POS-1 downto 0); + signal m_axis_decoded_tdata_bpmid : std_logic_vector(C_W_BPMID-1 downto 0); + signal m_axis_decoded_tdata_faseq : std_logic_vector(C_W_SEQ-1 downto 0); + + signal m_axis_filt_tdata : std_logic_vector(2*C_W_POS+C_W_BPMID+C_W_SEQ-1 downto 0); begin @@ -253,7 +262,12 @@ begin pps => pps_resync, gt_datarx => gt_datarx, - m_axis_m2s => m_axis_decoded_m2s, + m_axis_tvalid => m_axis_decoded_tvalid, + m_axis_tdata_posx => m_axis_decoded_tdata_posx, + m_axis_tdata_posy => m_axis_decoded_tdata_posy, + m_axis_tdata_bpmid => m_axis_decoded_tdata_bpmid, + m_axis_tdata_faseq => m_axis_decoded_tdata_faseq, + m_axis_tuser_mcts => open, mc_time => mc_time, soft_reset => addrmap_r.RESET.SOFTRESET.data(0), @@ -268,6 +282,10 @@ begin flag_reset => addrmap_r.RESET_ERROR.SOFTRESET.data(0) ); + -- Pack fo convenience + m_axis_decoded_tdata <= m_axis_decoded_tdata_posx & m_axis_decoded_tdata_posy & + m_axis_decoded_tdata_bpmid & m_axis_decoded_tdata_faseq; + --------------- -- GT WIZARD -- --------------- @@ -349,7 +367,8 @@ begin ------------------- inst_filter:entity work.combpm_packet_filter generic map( - G_W_ADDR_TABLE => C_W_ADDR_TABLE + G_W_ADDR_TABLE => C_W_ADDR_TABLE, + G_W_TDATA => m_axis_decoded_tdata'length ) port map( axis_clk => usrclk, @@ -357,13 +376,13 @@ begin axis_rst_n => sync_resetn, -- AXIS SLAVE INTERFACE - s_axis_tdest => m_axis_decoded_m2s.tdest, - s_axis_tdata => m_axis_decoded_m2s.tdata, - s_axis_tvalid => m_axis_decoded_m2s.tvalid, + s_axis_tdata => m_axis_decoded_tdata, + s_axis_tuser_bpmid => m_axis_decoded_tdata_bpmid, + s_axis_tvalid => m_axis_decoded_tvalid, -- AXIS SLAVE INTERFACE m_axis_tdest => m_axis_tdest, - m_axis_tdata => m_axis_tdata, + m_axis_tdata => m_axis_tdata_filt, m_axis_tvalid => m_axis_tvalid, -- Table configuration interface @@ -375,4 +394,10 @@ begin ); addrmap_w.filtertable.data(31 downto 8) <= (others => '0'); + -- unpack + m_axis_tdata_posx <= m_axis_filt_tdata(2*C_W_POS+C_W_BPMID+C_W_SEQ-1 downto C_W_POS+C_W_BPMID+C_W_SEQ); + m_axis_tdata_posy <= m_axis_filt_tdata(C_W_POS+C_W_BPMID+C_W_SEQ-1 downto C_W_BPMID+C_W_SEQ); + m_axis_tdata_bpmid <= m_axis_filt_tdata(C_W_BPMID+C_W_SEQ-1 downto C_W_SEQ); + m_axis_tdata_seq <= m_axis_filt_tdata(C_W_SEQ-1 downto 0); + end architecture struct; diff --git a/tcl/main.tcl b/tcl/main.tcl index 981ca440c5806ab0810232975df8a10f40d71bc9..60e90b0ce2afe44d04133695851501668d8e168a 100644 --- a/tcl/main.tcl +++ b/tcl/main.tcl @@ -24,7 +24,6 @@ proc setSources {} { lappend Vhdl ../hdl/pkg_combpm.vhd lappend Vhdl ../hdl/combpm_protocol_electron.vhd lappend Vhdl ../hdl/top_combpm_electron.vhd - lappend Vhdl ../hdl/pkg_bpmpacket_stream.vhd lappend Vhdl ../hdl/combpm_packet_filter.vhd }