From 868e8f6bfaeffc55c5e5462cb0daed44a5028807 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Romain=20Bron=C3=A8s?= <romain.brones@synchrotron-soleil.fr>
Date: Mon, 23 Oct 2023 16:47:02 +0200
Subject: [PATCH] feat(RDL): Update control/status registers layout
* Break sw R/RW registers, for OPCUA/ChimeraTK compatibility
* No behavioral change
---
hdl/top_combpm_electron.vhd | 48 ++++++++++-----------
rdl/combpm.rdl | 85 ++++++++++++++-----------------------
2 files changed, 56 insertions(+), 77 deletions(-)
diff --git a/hdl/top_combpm_electron.vhd b/hdl/top_combpm_electron.vhd
index 83b9a7c..69508b4 100644
--- a/hdl/top_combpm_electron.vhd
+++ b/hdl/top_combpm_electron.vhd
@@ -200,28 +200,28 @@ begin
src_in => cdc_control_array_axi
);
- addrmap_w.SFP.RXLOS.data(0) <= cdc_status_array_axi(0);
- addrmap_w.SFP.MODABS.data(0) <= cdc_status_array_axi(1);
- addrmap_w.GT.POWERGOOD.data(0) <= cdc_status_array_axi(2);
- addrmap_w.GT.QPLLLOCK.data(0) <= cdc_status_array_axi(3);
- addrmap_w.GT.RXCDRLOCK.data(0) <= cdc_status_array_axi(4);
- addrmap_w.GT.RXRESETDONE.data(0) <= cdc_status_array_axi(5);
- addrmap_w.GT.RXBYTEISALIGNED.data(0) <= cdc_status_array_axi(6);
- addrmap_w.GT.RXBYTEREALIGN.data(0) <= cdc_status_array_axi(7);
- addrmap_w.GT.RXCOMMADET.data(0) <= cdc_status_array_axi(8);
- addrmap_w.PROTOCOL.FRAMEERROR.data(0) <= cdc_status_array_axi(9);
- addrmap_w.PROTOCOL.SEQFRAMECNTERROR.data(0) <= cdc_status_array_axi(10);
- addrmap_w.PROTOCOL.SEQFRAMEDISCONT.data(0) <= cdc_status_array_axi(11);
-
- addrmap_w.VALIDFRAMECNT.data.data <= cdc_status_array_axi(43 downto 12);
- addrmap_w.INVALIDFRAMECNT.data.data <= cdc_status_array_axi(75 downto 44);
- addrmap_w.VALIDFRAMERATE.data.data <= cdc_status_array_axi(107 downto 76);
- addrmap_w.INVALIDFRAMERATE.data.data <= cdc_status_array_axi(139 downto 108);
- addrmap_w.FRAMESEQ.data.data <= cdc_status_array_axi(155 downto 140);
-
- cdc_control_array_axi(0) <= addrmap_r.GT.RXRSTDATAPATH.data(0);
- cdc_control_array_axi(1) <= addrmap_r.GT.RXRSTPLLDATAPATH.data(0);
- cdc_control_array_axi(2) <= addrmap_r.GT.RXCOMMADETEN.data(0);
+ addrmap_w.SFP.RXLOS.data(0) <= cdc_status_array_axi(0);
+ addrmap_w.SFP.MODABS.data(0) <= cdc_status_array_axi(1);
+ addrmap_w.GT_STATUS.POWERGOOD.data(0) <= cdc_status_array_axi(2);
+ addrmap_w.GT_STATUS.QPLLLOCK.data(0) <= cdc_status_array_axi(3);
+ addrmap_w.GT_STATUS.RXCDRLOCK.data(0) <= cdc_status_array_axi(4);
+ addrmap_w.GT_STATUS.RXRESETDONE.data(0) <= cdc_status_array_axi(5);
+ addrmap_w.GT_STATUS.RXBYTEISALIGNED.data(0) <= cdc_status_array_axi(6);
+ addrmap_w.GT_STATUS.RXBYTEREALIGN.data(0) <= cdc_status_array_axi(7);
+ addrmap_w.GT_STATUS.RXCOMMADET.data(0) <= cdc_status_array_axi(8);
+ addrmap_w.PROTOCOL_ERROR.FRAMEERROR.data(0) <= cdc_status_array_axi(9);
+ addrmap_w.PROTOCOL_ERROR.SEQFRAMECNTERROR.data(0) <= cdc_status_array_axi(10);
+ addrmap_w.PROTOCOL_ERROR.SEQFRAMEDISCONT.data(0) <= cdc_status_array_axi(11);
+
+ addrmap_w.VALIDFRAMECNT.data.data <= cdc_status_array_axi(43 downto 12);
+ addrmap_w.INVALIDFRAMECNT.data.data <= cdc_status_array_axi(75 downto 44);
+ addrmap_w.VALIDFRAMERATE.data.data <= cdc_status_array_axi(107 downto 76);
+ addrmap_w.INVALIDFRAMERATE.data.data <= cdc_status_array_axi(139 downto 108);
+ addrmap_w.FRAMESEQ.data.data <= cdc_status_array_axi(155 downto 140);
+
+ cdc_control_array_axi(0) <= addrmap_r.GT_CONTROL.RXRSTDATAPATH.data(0);
+ cdc_control_array_axi(1) <= addrmap_r.GT_CONTROL.RXRSTPLLDATAPATH.data(0);
+ cdc_control_array_axi(2) <= addrmap_r.GT_CONTROL.RXCOMMADETEN.data(0);
end block blk_desyrdl;
@@ -238,7 +238,7 @@ begin
m_axis_m2s => m_axis_decoded_m2s,
mc_time => mc_time,
- soft_reset => addrmap_w.PROTOCOL.SOFTRESET.data(0),
+ soft_reset => addrmap_w.RESET.SOFTRESET.data(0),
frame_seq_cnt => frame_seq_cnt,
frame_valid_cnt => frame_valid_cnt,
frame_invalid_cnt => frame_invalid_cnt,
@@ -287,7 +287,7 @@ begin
-- Status
gtwiz_userclk_tx_active_out => open,
- gtwiz_userclk_rx_active_out => addrmap_w.GT.RXCLKACTIVE.data,
+ gtwiz_userclk_rx_active_out => addrmap_w.GT_STATUS.RXCLKACTIVE.data,
gtwiz_reset_tx_done_out => open,
gtwiz_reset_rx_done_out(0) => gt_rxresetdone,
gtpowergood_out(0) => gt_powergood,
diff --git a/rdl/combpm.rdl b/rdl/combpm.rdl
index 4cd1004..8fabb38 100644
--- a/rdl/combpm.rdl
+++ b/rdl/combpm.rdl
@@ -10,12 +10,11 @@ addrmap combpm {
desyrdl_interface = "AXI4L";
- reg {
+ reg {
desc="Module Identification Number";
- default sw = r;
- default hw = r;
+ default sw = r; default hw = r;
field {} data[32] = `C_ID;
- } ID @0x00;
+ } ID @0x00;
reg {
desc="Module version.";
@@ -33,61 +32,41 @@ addrmap combpm {
} SFP;
reg {
- desc="GT transceivers status and control";
+ desc="GT transceivers status";
desyrdl_data_type="bitfields";
+ default sw = r; default hw = w;
+ field {desc="Powergood signal";} POWERGOOD;
+ field {desc="PLL lock signal";} QPLLLOCK;
+ field {desc="RX clk active signal";} RXCLKACTIVE;
+ field {desc="RX CDR lock signal";} RXCDRLOCK;
+ field {desc="RX reset done signal";} RXRESETDONE;
+ field {desc="RX byte is aligned signal";} RXBYTEISALIGNED;
+ field {desc="RX byte realign signal";} RXBYTEREALIGN;
+ field {desc="RX comma detected signal";} RXCOMMADET;
+ } GT_STATUS;
- field {desc="Powergood signal";hw=w;sw=r;
- } POWERGOOD;
-
- field {desc="PLL lock signal";hw=w;sw=r;
- } QPLLLOCK;
-
- field {desc="RX clk active signal";hw=w;sw=r;
- } RXCLKACTIVE;
-
- field {desc="RX CDR lock signal";hw=w;sw=r;
- } RXCDRLOCK;
-
- field {desc="RX reset done signal";hw=w;sw=r;
- } RXRESETDONE;
-
- field {desc="RX byte is aligned signal";hw=w;sw=r;
- } RXBYTEISALIGNED;
-
- field {desc="RX byte realign signal";hw=w;sw=r;
- } RXBYTEREALIGN;
-
- field {desc="RX comma detected signal";hw=w;sw=r;
- } RXCOMMADET;
-
- field {desc="RX comma detection enable signal";hw=r;sw=rw;
- } RXCOMMADETEN = 1;
-
- field {desc="Reset RX datapath";hw=r;sw=rw;
- } RXRSTDATAPATH = 1;
-
- field {desc="Reset RX PLL and datapath";hw=r;sw=rw;
- } RXRSTPLLDATAPATH = 1;
-
- } GT;
+ reg {
+ desc="GT transceivers control";
+ desyrdl_data_type="bitfields";
+ default sw = rw; default hw = r;
+ field {desc="RX comma detection enable signal";} RXCOMMADETEN = 1;
+ field {desc="Reset RX datapath";} RXRSTDATAPATH = 1;
+ field {desc="Reset RX PLL and datapath";} RXRSTPLLDATAPATH = 1;
+ } GT_CONTROL;
reg {
desc="BPM protocol status and control";
desyrdl_data_type="bitfields";
-
- field {desc="Frame error";hw=w;sw=r;
- } FRAMEERROR;
-
- field {desc="Sequence frame count mismatch";hw=w;sw=r;
- } SEQFRAMECNTERROR;
-
- field {desc="Sequence frame discontinuity";hw=w;sw=r;
- } SEQFRAMEDISCONT;
-
- field {desc="Soft reset";hw=r;sw=rw;
- } SOFTRESET;
-
- } PROTOCOL;
+ default sw = r; default hw = w;
+ field {desc="Frame error";} FRAMEERROR;
+ field {desc="Sequence frame count mismatch";} SEQFRAMECNTERROR;
+ field {desc="Sequence frame discontinuity";} SEQFRAMEDISCONT;
+ } PROTOCOL_ERROR;
+
+ reg {
+ default sw = rw; default hw = r;
+ field {desc="Soft reset";} SOFTRESET;
+ } RESET;
reg {
desc="BPM protocol valid frame counters";
--
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