diff --git a/hdl/top_combpm_electron.vhd b/hdl/top_combpm_electron.vhd
index 7348f4e4cfb8ac132b0071adead2d8010bf74d1f..79357ccb78bf7b8b1dcf4702bbb03ed456a56bcd 100644
--- a/hdl/top_combpm_electron.vhd
+++ b/hdl/top_combpm_electron.vhd
@@ -8,28 +8,24 @@ use ieee.numeric_std.all;
entity top_combpm_electron is
port(
- clk : in std_logic;
+ clk_gt : out std_logic; -- Clock ref from GT
rst_n : in std_logic;
+ clk_100 : in std_logic; -- Freerunning clock for GT
- -- GT interface
- gt_datarx : in std_logic_vector(15 downto 0);
- gt_datatx : out std_logic_vector(15 downto 0);
- gt_powergood : in std_logic;
- gt_qplllock : in std_logic;
- gt_txclkactive : in std_logic;
- gt_rxclkactive : in std_logic;
- gt_txresetdone : in std_logic;
- gt_rxresetdone : in std_logic;
- gt_rxcdrlock : in std_logic;
- gt_rxbyteisaligned : in std_logic;
- gt_rxbyterealign : in std_logic;
- gt_rxcommadet : in std_logic;
- gt_txfault : in std_logic;
- gt_rxlos : in std_logic;
- gt_modabs : in std_logic;
- gt_rstall : out std_logic;
- gt_rxcommadeten : out std_logic;
- gt_txdisable : out std_logic;
+ -- Differential reference clock inputs and buffered output
+ mgtrefclk_p : in std_logic;
+ mgtrefclk_n : in std_logic;
+ mgtrefclk : out std_logic;
+
+ -- SFP interfaces
+ sfp_txp : out std_logic;
+ sfp_txn : out std_logic;
+ sfp_rxp : in std_logic;
+ sfp_rxn : in std_logic;
+ sfp_rx_los : in std_logic;
+ sfp_mod_abs : in std_logic;
+ sfp_tx_disable : out std_logic;
+ sfp_tx_fault : in std_logic;
-- AXIS interface
m_axi_tid : out std_logic_vector(0 downto 0);
@@ -83,25 +79,6 @@ architecture struct of top_combpm_electron is
ATTRIBUTE X_INTERFACE_INFO of m_axi_tvalid : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TVALID";
ATTRIBUTE X_INTERFACE_INFO of m_axi_tready : SIGNAL is "xilinx.com:interface:axis:1.0 M_AXI TREADY";
- ATTRIBUTE X_INTERFACE_INFO of gt_datarx : SIGNAL is "soleil:user:gtsfp:1.0 GT datarx";
- ATTRIBUTE X_INTERFACE_INFO of gt_datatx : SIGNAL is "soleil:user:gtsfp:1.0 GT datatx";
- ATTRIBUTE X_INTERFACE_INFO of gt_powergood : SIGNAL is "soleil:user:gtsfp:1.0 GT powergood";
- ATTRIBUTE X_INTERFACE_INFO of gt_qplllock : SIGNAL is "soleil:user:gtsfp:1.0 GT qplllock";
- ATTRIBUTE X_INTERFACE_INFO of gt_txclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT txclkactive";
- ATTRIBUTE X_INTERFACE_INFO of gt_rxclkactive : SIGNAL is "soleil:user:gtsfp:1.0 GT rxclkactive";
- ATTRIBUTE X_INTERFACE_INFO of gt_txresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT txresetdone";
- ATTRIBUTE X_INTERFACE_INFO of gt_rxresetdone : SIGNAL is "soleil:user:gtsfp:1.0 GT rxresetdone";
- ATTRIBUTE X_INTERFACE_INFO of gt_rxcdrlock : SIGNAL is "soleil:user:gtsfp:1.0 GT rxcdrlock";
- ATTRIBUTE X_INTERFACE_INFO of gt_rxbyteisaligned : SIGNAL is "soleil:user:gtsfp:1.0 GT rxbyteisaligned";
- ATTRIBUTE X_INTERFACE_INFO of gt_rxbyterealign : SIGNAL is "soleil:user:gtsfp:1.0 GT rxbyterealign";
- ATTRIBUTE X_INTERFACE_INFO of gt_rxcommadet : SIGNAL is "soleil:user:gtsfp:1.0 GT rxcommadet";
- ATTRIBUTE X_INTERFACE_INFO of gt_txfault : SIGNAL is "soleil:user:gtsfp:1.0 GT txfault";
- ATTRIBUTE X_INTERFACE_INFO of gt_rxlos : SIGNAL is "soleil:user:gtsfp:1.0 GT rxlos";
- ATTRIBUTE X_INTERFACE_INFO of gt_modabs : SIGNAL is "soleil:user:gtsfp:1.0 GT modabs";
- ATTRIBUTE X_INTERFACE_INFO of gt_rstall : SIGNAL is "soleil:user:gtsfp:1.0 GT rstall";
- ATTRIBUTE X_INTERFACE_INFO of gt_rxcommadeten : SIGNAL is "soleil:user:gtsfp:1.0 GT rxcommadeten";
- ATTRIBUTE X_INTERFACE_INFO of gt_txdisable : SIGNAL is "soleil:user:gtsfp:1.0 GT txdisable";
-
ATTRIBUTE X_INTERFACE_INFO of rst_n : SIGNAL is "xilinx.com:signal:reset:1.0 rst_n RST";
ATTRIBUTE X_INTERFACE_PARAMETER of rst_n : SIGNAL is "POLARITY ACTIVE_LOW";
@@ -115,11 +92,33 @@ architecture struct of top_combpm_electron is
signal frame_counter : std_logic_vector(15 downto 0);
signal frame_error : std_logic;
+ signal gt_userclk : std_logic;
+ signal gt_datarx : std_logic_vector(15 downto 0);
+ signal gt_datatx : std_logic_vector(15 downto 0);
+ signal gt_powergood : std_logic;
+ signal gt_qplllock : std_logic;
+ signal gt_txclkactive : std_logic;
+ signal gt_rxclkactive : std_logic;
+ signal gt_txresetdone : std_logic;
+ signal gt_rxresetdone : std_logic;
+ signal gt_rxbyteisaligned : std_logic;
+ signal gt_rxbyterealign : std_logic;
+ signal gt_rxcommadet : std_logic;
+ signal gt_txfault : std_logic;
+ signal gt_rxlos : std_logic;
+ signal gt_modabs : std_logic;
+ signal gt_rstall : std_logic;
+ signal gt_rxcommadeten : std_logic;
+ signal gt_txdisable : std_logic;
+
begin
-- Reset invert polarity
rst <= not rst_n;
+ ----------------------
+ -- AXI-MM INTERFACE --
+ ----------------------
axiitf_inst: entity work.combpm_protocol_electron_ctrl_axi
generic map(
G_ADDR_W => 8
@@ -144,7 +143,7 @@ begin
protocol_framecnt_i => frame_counter,
protocol_frameerror_i => frame_error,
- clk => clk,
+ clk => gt_usrclk,
reset => rst,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWPROT => S_AXI_AWPROT,
@@ -167,10 +166,13 @@ begin
S_AXI_RREADY => S_AXI_RREADY
);
+ --------------------------------------
+ -- LIBERA ELECTRON PROCOTOL DECODER --
+ --------------------------------------
protocol_inst: entity work.combpm_protocol_electron
port map(
rst_n => rst_n,
- clk => clk,
+ clk => gt_userclk,
gt_datarx => gt_datarx,
gt_datatx => gt_datatx,
gt_powergood => gt_powergood,
@@ -208,5 +210,55 @@ begin
);
+ ----------------
+ -- GT WRAPPER --
+ ----------------
+ clk_gt <= gt_userclk;
+ inst_gtwrapper: entity work.combpm_gtwrapper
+ port map(
+ -- 100MHz clock, main ref clock
+ clk_100 => clk_100,
+
+ -- Usrclock for data transfer
+ usrclk => gt_userclk,
+
+ -- Async reset active low
+ rst_n => rst_n,
+
+ -- Differential reference clock inputs and buffered output
+ mgtrefclk_p => mgtrefclk_p,
+ mgtrefclk_n => mgtrefclk_n,
+ mgtrefclk => open,
+
+ -- SFP interfaces
+ sfp_txp(0) => sfp_txp,
+ sfp_txn(0) => sfp_txn,
+ sfp_rxp(0) => sfp_rxp,
+ sfp_rxn(0) => sfp_rxn,
+ sfp_rx_los(0) => sfp_rx_los,
+ sfp_mod_abs(0) => sfp_mod_abs,
+ sfp_tx_disable(0) => sfp_tx_disable,
+ sfp_tx_fault(0) => sfp_tx_fault,
+
+ -- GT interfaces
+ gt_datarx => gt_datarx,
+ gt_datatx => gt_datatx,
+ gt_powergood(0) => gt_powergood,
+ gt_qplllock(0) => gt_qplllock,
+ gt_txclkactive(0) => gt_txclkactive,
+ gt_rxclkactive(0) => gt_rxclkactive,
+ gt_txresetdone(0) => gt_txresetdone,
+ gt_rxresetdone(0) => gt_rxresetdone,
+ gt_rxbyteisaligned(0) => gt_rxbyteisaligned,
+ gt_rxbyterealign(0) => gt_rxbyterealign,
+ gt_rxcommadet(0) => gt_rxcommadet,
+ gt_txfault(0) => gt_txfault,
+ gt_rxlos(0) => gt_rxlos,
+ gt_modabs(0) => gt_modabs,
+ gt_rstall(0) => gt_rstall,
+ gt_rxcommadeten(0) => gt_rxcommadeten,
+ gt_txdisable(0) => gt_txdisable
+ );
+
end architecture struct;
diff --git a/tcl/combpm.tcl b/tcl/combpm.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..7a33f75dbf91c8be86f9554f139bcbc52d93fdf0
--- /dev/null
+++ b/tcl/combpm.tcl
@@ -0,0 +1,32 @@
+# Source metadata
+source ./tcl/metadata.tcl
+
+# Create project
+set ip_project [ create_project -name ${design} -force -dir ${proj_dir} -ip -part ${part} ]
+set_property top ${top} [current_fileset]
+
+# Compilation order in auto
+set_property source_mgmt_mode All ${ip_project}
+
+# Read source files
+read_vhdl "hdl/top_combpm_electron.vhd"
+read_vhdl "hdl/combpm_protocol_electron.vhd"
+read_vhdl "hdl/combpm_protocol_electron_ctrl.vhd"
+read_vhdl "hdl/combpm_gtwrapper.vhd"
+read_vhdl "hdl/combpm_gtwrapper_CAENELS4SFP_1L_pkg.vhd"
+import_ip -name combpm_gtwrapper "ip_cores/CAENELSSFP_1L.xci"
+update_compile_order -fileset sources_1
+
+# Package project
+ipx::package_project
+set ip_core [ipx::current_core]
+set_property -dict ${ip_properties} ${ip_core}
+set_property SUPPORTED_FAMILIES ${family_lifecycle} ${ip_core}
+
+# Associate AX/AXIS interfaces and reset with clock
+# Later... or in HDL
+
+ # Save IP and close project
+ipx::check_integrity ${ip_core}
+ipx::save_core ${ip_core}
+close_project
diff --git a/tcl/metadata.tcl b/tcl/metadata.tcl
new file mode 100644
index 0000000000000000000000000000000000000000..19e2dabe6526e039f41ce690655ecda91a8e1ff9
--- /dev/null
+++ b/tcl/metadata.tcl
@@ -0,0 +1,20 @@
+set design "combpm"
+set top top_combpm_electron
+set proj_dir "./ip_proj"
+set part "xczu11eg-ffvc1760-2L-e"
+
+set ip_properties [ list \
+ vendor "synchrotron-soleil.fr" \
+ library "fofb" \
+ name ${design} \
+ version "1.0" \
+ taxonomy "/transceiver" \
+ display_name "Electron Communication Decoder" \
+ description "Decode CC protocol from a transceiver interface and generate AXIS frames" \
+ vendor_display_name "Synchrotron SOLEIL" \
+ company_url "" \
+ ]
+
+set family_lifecycle { \
+ zynquplus Beta \
+}