diff --git a/Makefile b/Makefile
index 45bc3d02a13b0112a97829b1fa47b775267f1750..6d32d8021040a2c68643f6562b1ad946c7057b12 100644
--- a/Makefile
+++ b/Makefile
@@ -2,7 +2,6 @@
# Global receipes
none:
$(info You should specify what to make: ip, sim, clean, clean-all)
-ip:component.xml
sim:
@@ -29,9 +28,12 @@ hdl/combpm_protocol_electron_ctrl.vhd: rdl/combpm_protocol_electron_ctrl.rdl
###############################################################################
# Package IP
+ip:component.xml
+
component.xml:tcl/sources.tcl tcl/combpm.tcl $(hdlsrc) $(xcisrc)
vivado -mode batch -source tcl/combpm.tcl
+
###############################################################################
# Cleaner Rules
clean:
@@ -46,5 +48,6 @@ clean-sim:
clean-all:clean-ip clean
rm -f tcl/sources.tcl
+ rm -f hdl/combpm_protocol_electron_ctrl.vhd
.PHONY: clean clean-ip clean-sim clean-all none ip sim
diff --git a/hdl/combpm_gtwizard_gthe4_common_wrapper.v b/hdl/combpm_gtwizard_gthe4_common_wrapper.v
new file mode 100644
index 0000000000000000000000000000000000000000..5085df4597ec33d6d573566bf1fe2e52ccef9cd3
--- /dev/null
+++ b/hdl/combpm_gtwizard_gthe4_common_wrapper.v
@@ -0,0 +1,397 @@
+
+
+`timescale 1ps/1ps
+module combpm_gtwizard_gthe4_common_wrapper (
+ input [0:0] GTHE4_COMMON_BGBYPASSB,
+ input [0:0] GTHE4_COMMON_BGMONITORENB,
+ input [0:0] GTHE4_COMMON_BGPDB,
+ input [4:0] GTHE4_COMMON_BGRCALOVRD,
+ input [0:0] GTHE4_COMMON_BGRCALOVRDENB,
+ input [15:0] GTHE4_COMMON_DRPADDR,
+ input [0:0] GTHE4_COMMON_DRPCLK,
+ input [15:0] GTHE4_COMMON_DRPDI,
+ input [0:0] GTHE4_COMMON_DRPEN,
+ input [0:0] GTHE4_COMMON_DRPWE,
+ input [0:0] GTHE4_COMMON_GTGREFCLK0,
+ input [0:0] GTHE4_COMMON_GTGREFCLK1,
+ input [0:0] GTHE4_COMMON_GTNORTHREFCLK00,
+ input [0:0] GTHE4_COMMON_GTNORTHREFCLK01,
+ input [0:0] GTHE4_COMMON_GTNORTHREFCLK10,
+ input [0:0] GTHE4_COMMON_GTNORTHREFCLK11,
+ input [0:0] GTHE4_COMMON_GTREFCLK00,
+ input [0:0] GTHE4_COMMON_GTREFCLK01,
+ input [0:0] GTHE4_COMMON_GTREFCLK10,
+ input [0:0] GTHE4_COMMON_GTREFCLK11,
+ input [0:0] GTHE4_COMMON_GTSOUTHREFCLK00,
+ input [0:0] GTHE4_COMMON_GTSOUTHREFCLK01,
+ input [0:0] GTHE4_COMMON_GTSOUTHREFCLK10,
+ input [0:0] GTHE4_COMMON_GTSOUTHREFCLK11,
+ input [2:0] GTHE4_COMMON_PCIERATEQPLL0,
+ input [2:0] GTHE4_COMMON_PCIERATEQPLL1,
+ input [7:0] GTHE4_COMMON_PMARSVD0,
+ input [7:0] GTHE4_COMMON_PMARSVD1,
+ input [0:0] GTHE4_COMMON_QPLL0CLKRSVD0,
+ input [0:0] GTHE4_COMMON_QPLL0CLKRSVD1,
+ input [7:0] GTHE4_COMMON_QPLL0FBDIV,
+ input [0:0] GTHE4_COMMON_QPLL0LOCKDETCLK,
+ input [0:0] GTHE4_COMMON_QPLL0LOCKEN,
+ input [0:0] GTHE4_COMMON_QPLL0PD,
+ input [2:0] GTHE4_COMMON_QPLL0REFCLKSEL,
+ input [0:0] GTHE4_COMMON_QPLL0RESET,
+ input [0:0] GTHE4_COMMON_QPLL1CLKRSVD0,
+ input [0:0] GTHE4_COMMON_QPLL1CLKRSVD1,
+ input [7:0] GTHE4_COMMON_QPLL1FBDIV,
+ input [0:0] GTHE4_COMMON_QPLL1LOCKDETCLK,
+ input [0:0] GTHE4_COMMON_QPLL1LOCKEN,
+ input [0:0] GTHE4_COMMON_QPLL1PD,
+ input [2:0] GTHE4_COMMON_QPLL1REFCLKSEL,
+ input [0:0] GTHE4_COMMON_QPLL1RESET,
+ input [7:0] GTHE4_COMMON_QPLLRSVD1,
+ input [4:0] GTHE4_COMMON_QPLLRSVD2,
+ input [4:0] GTHE4_COMMON_QPLLRSVD3,
+ input [7:0] GTHE4_COMMON_QPLLRSVD4,
+ input [0:0] GTHE4_COMMON_RCALENB,
+ input [24:0] GTHE4_COMMON_SDM0DATA,
+ input [0:0] GTHE4_COMMON_SDM0RESET,
+ input [0:0] GTHE4_COMMON_SDM0TOGGLE,
+ input [1:0] GTHE4_COMMON_SDM0WIDTH,
+ input [24:0] GTHE4_COMMON_SDM1DATA,
+ input [0:0] GTHE4_COMMON_SDM1RESET,
+ input [0:0] GTHE4_COMMON_SDM1TOGGLE,
+ input [1:0] GTHE4_COMMON_SDM1WIDTH,
+ input [9:0] GTHE4_COMMON_TCONGPI,
+ input [0:0] GTHE4_COMMON_TCONPOWERUP,
+ input [1:0] GTHE4_COMMON_TCONRESET,
+ input [1:0] GTHE4_COMMON_TCONRSVDIN1,
+
+ output [15:0] GTHE4_COMMON_DRPDO,
+ output [0:0] GTHE4_COMMON_DRPRDY,
+ output [7:0] GTHE4_COMMON_PMARSVDOUT0,
+ output [7:0] GTHE4_COMMON_PMARSVDOUT1,
+ output [0:0] GTHE4_COMMON_QPLL0FBCLKLOST,
+ output [0:0] GTHE4_COMMON_QPLL0LOCK,
+ output [0:0] GTHE4_COMMON_QPLL0OUTCLK,
+ output [0:0] GTHE4_COMMON_QPLL0OUTREFCLK,
+ output [0:0] GTHE4_COMMON_QPLL0REFCLKLOST,
+ output [0:0] GTHE4_COMMON_QPLL1FBCLKLOST,
+ output [0:0] GTHE4_COMMON_QPLL1LOCK,
+ output [0:0] GTHE4_COMMON_QPLL1OUTCLK,
+ output [0:0] GTHE4_COMMON_QPLL1OUTREFCLK,
+ output [0:0] GTHE4_COMMON_QPLL1REFCLKLOST,
+ output [7:0] GTHE4_COMMON_QPLLDMONITOR0,
+ output [7:0] GTHE4_COMMON_QPLLDMONITOR1,
+ output [0:0] GTHE4_COMMON_REFCLKOUTMONITOR0,
+ output [0:0] GTHE4_COMMON_REFCLKOUTMONITOR1,
+ output [1:0] GTHE4_COMMON_RXRECCLK0SEL,
+ output [1:0] GTHE4_COMMON_RXRECCLK1SEL,
+ output [3:0] GTHE4_COMMON_SDM0FINALOUT,
+ output [14:0] GTHE4_COMMON_SDM0TESTDATA,
+ output [3:0] GTHE4_COMMON_SDM1FINALOUT,
+ output [14:0] GTHE4_COMMON_SDM1TESTDATA,
+ output [9:0] GTHE4_COMMON_TCONGPO,
+ output [0:0] GTHE4_COMMON_TCONRSVDOUT0
+);
+
+
+
+gtwizard_ultrascale_v1_7_9_gthe4_common #(
+ .GTHE4_COMMON_AEN_QPLL0_FBDIV (1'b1),
+ .GTHE4_COMMON_AEN_QPLL1_FBDIV (1'b1),
+ .GTHE4_COMMON_AEN_SDM0TOGGLE (1'b0),
+ .GTHE4_COMMON_AEN_SDM1TOGGLE (1'b0),
+ .GTHE4_COMMON_A_SDM0TOGGLE (1'b0),
+ .GTHE4_COMMON_A_SDM1DATA_HIGH (9'b000000000),
+ .GTHE4_COMMON_A_SDM1DATA_LOW (16'b0000000000000000),
+ .GTHE4_COMMON_A_SDM1TOGGLE (1'b0),
+ .GTHE4_COMMON_BGBYPASSB_TIE_EN (1'b0),
+ .GTHE4_COMMON_BGBYPASSB_VAL (1'b1),
+ .GTHE4_COMMON_BGMONITORENB_TIE_EN (1'b0),
+ .GTHE4_COMMON_BGMONITORENB_VAL (1'b1),
+ .GTHE4_COMMON_BGPDB_TIE_EN (1'b0),
+ .GTHE4_COMMON_BGPDB_VAL (1'b1),
+ .GTHE4_COMMON_BGRCALOVRDENB_TIE_EN (1'b0),
+ .GTHE4_COMMON_BGRCALOVRDENB_VAL (1'b1),
+ .GTHE4_COMMON_BGRCALOVRD_TIE_EN (1'b0),
+ .GTHE4_COMMON_BGRCALOVRD_VAL (5'b11111),
+ .GTHE4_COMMON_BIAS_CFG0 (16'b0000000000000000),
+ .GTHE4_COMMON_BIAS_CFG1 (16'b0000000000000000),
+ .GTHE4_COMMON_BIAS_CFG2 (16'b0000000100100100),
+ .GTHE4_COMMON_BIAS_CFG3 (16'b0000000001000001),
+ .GTHE4_COMMON_BIAS_CFG4 (16'b0000000000010000),
+ .GTHE4_COMMON_BIAS_CFG_RSVD (16'b0000000000000000),
+ .GTHE4_COMMON_COMMON_CFG0 (16'b0000000000000000),
+ .GTHE4_COMMON_COMMON_CFG1 (16'b0000000000000000),
+ .GTHE4_COMMON_DRPADDR_TIE_EN (1'b0),
+ .GTHE4_COMMON_DRPADDR_VAL (16'b0000000000000000),
+ .GTHE4_COMMON_DRPCLK_TIE_EN (1'b0),
+ .GTHE4_COMMON_DRPCLK_VAL (1'b0),
+ .GTHE4_COMMON_DRPDI_TIE_EN (1'b0),
+ .GTHE4_COMMON_DRPDI_VAL (16'b0000000000000000),
+ .GTHE4_COMMON_DRPEN_TIE_EN (1'b0),
+ .GTHE4_COMMON_DRPEN_VAL (1'b0),
+ .GTHE4_COMMON_DRPWE_TIE_EN (1'b0),
+ .GTHE4_COMMON_DRPWE_VAL (1'b0),
+ .GTHE4_COMMON_GTGREFCLK0_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTGREFCLK0_VAL (1'b0),
+ .GTHE4_COMMON_GTGREFCLK1_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTGREFCLK1_VAL (1'b0),
+ .GTHE4_COMMON_GTNORTHREFCLK00_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTNORTHREFCLK00_VAL (1'b0),
+ .GTHE4_COMMON_GTNORTHREFCLK01_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTNORTHREFCLK01_VAL (1'b0),
+ .GTHE4_COMMON_GTNORTHREFCLK10_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTNORTHREFCLK10_VAL (1'b0),
+ .GTHE4_COMMON_GTNORTHREFCLK11_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTNORTHREFCLK11_VAL (1'b0),
+ .GTHE4_COMMON_GTREFCLK00_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTREFCLK00_VAL (1'b0),
+ .GTHE4_COMMON_GTREFCLK01_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTREFCLK01_VAL (1'b0),
+ .GTHE4_COMMON_GTREFCLK10_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTREFCLK10_VAL (1'b0),
+ .GTHE4_COMMON_GTREFCLK11_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTREFCLK11_VAL (1'b0),
+ .GTHE4_COMMON_GTSOUTHREFCLK00_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTSOUTHREFCLK00_VAL (1'b0),
+ .GTHE4_COMMON_GTSOUTHREFCLK01_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTSOUTHREFCLK01_VAL (1'b0),
+ .GTHE4_COMMON_GTSOUTHREFCLK10_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTSOUTHREFCLK10_VAL (1'b0),
+ .GTHE4_COMMON_GTSOUTHREFCLK11_TIE_EN (1'b0),
+ .GTHE4_COMMON_GTSOUTHREFCLK11_VAL (1'b0),
+ .GTHE4_COMMON_PCIERATEQPLL0_TIE_EN (1'b0),
+ .GTHE4_COMMON_PCIERATEQPLL0_VAL (3'b000),
+ .GTHE4_COMMON_PCIERATEQPLL1_TIE_EN (1'b0),
+ .GTHE4_COMMON_PCIERATEQPLL1_VAL (3'b000),
+ .GTHE4_COMMON_PMARSVD0_TIE_EN (1'b0),
+ .GTHE4_COMMON_PMARSVD0_VAL (8'b00000000),
+ .GTHE4_COMMON_PMARSVD1_TIE_EN (1'b0),
+ .GTHE4_COMMON_PMARSVD1_VAL (8'b00000000),
+ .GTHE4_COMMON_POR_CFG (16'b0000000000000000),
+ .GTHE4_COMMON_PPF0_CFG (16'b0000011000000000),
+ .GTHE4_COMMON_PPF1_CFG (16'b0000011000000000),
+ .GTHE4_COMMON_QPLL0CLKOUT_RATE ("HALF"),
+ .GTHE4_COMMON_QPLL0CLKRSVD0_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL0CLKRSVD0_VAL (1'b0),
+ .GTHE4_COMMON_QPLL0CLKRSVD1_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL0CLKRSVD1_VAL (1'b0),
+ .GTHE4_COMMON_QPLL0FBDIV_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL0FBDIV_VAL (8'b00000000),
+ .GTHE4_COMMON_QPLL0LOCKDETCLK_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL0LOCKDETCLK_VAL (1'b0),
+ .GTHE4_COMMON_QPLL0LOCKEN_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL0LOCKEN_VAL (1'b1),
+ .GTHE4_COMMON_QPLL0PD_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL0PD_VAL (1'b0),
+ .GTHE4_COMMON_QPLL0REFCLKSEL_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL0REFCLKSEL_VAL (3'b001),
+ .GTHE4_COMMON_QPLL0RESET_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL0RESET_VAL (1'b0),
+ .GTHE4_COMMON_QPLL0_CFG0 (16'b0011001100011100),
+ .GTHE4_COMMON_QPLL0_CFG1 (16'b1101000000111000),
+ .GTHE4_COMMON_QPLL0_CFG1_G3 (16'b1101000000111000),
+ .GTHE4_COMMON_QPLL0_CFG2 (16'b0000111111000000),
+ .GTHE4_COMMON_QPLL0_CFG2_G3 (16'b0000111111000000),
+ .GTHE4_COMMON_QPLL0_CFG3 (16'b0000000100100000),
+ .GTHE4_COMMON_QPLL0_CFG4 (16'b0000000000000011),
+ .GTHE4_COMMON_QPLL0_CP (10'b0011111111),
+ .GTHE4_COMMON_QPLL0_CP_G3 (10'b0000001111),
+ .GTHE4_COMMON_QPLL0_FBDIV (66),
+ .GTHE4_COMMON_QPLL0_FBDIV_G3 (160),
+ .GTHE4_COMMON_QPLL0_INIT_CFG0 (16'b0000001010110010),
+ .GTHE4_COMMON_QPLL0_INIT_CFG1 (8'b00000000),
+ .GTHE4_COMMON_QPLL0_LOCK_CFG (16'b0010010111101000),
+ .GTHE4_COMMON_QPLL0_LOCK_CFG_G3 (16'b0010010111101000),
+ .GTHE4_COMMON_QPLL0_LPF (10'b1000111111),
+ .GTHE4_COMMON_QPLL0_LPF_G3 (10'b0111010101),
+ .GTHE4_COMMON_QPLL0_PCI_EN (1'b0),
+ .GTHE4_COMMON_QPLL0_RATE_SW_USE_DRP (1'b1),
+ .GTHE4_COMMON_QPLL0_REFCLK_DIV (1),
+ .GTHE4_COMMON_QPLL0_SDM_CFG0 (16'b0000000010000000),
+ .GTHE4_COMMON_QPLL0_SDM_CFG1 (16'b0000000000000000),
+ .GTHE4_COMMON_QPLL0_SDM_CFG2 (16'b0000000000000000),
+ .GTHE4_COMMON_QPLL1CLKOUT_RATE ("HALF"),
+ .GTHE4_COMMON_QPLL1CLKRSVD0_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL1CLKRSVD0_VAL (1'b0),
+ .GTHE4_COMMON_QPLL1CLKRSVD1_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL1CLKRSVD1_VAL (1'b0),
+ .GTHE4_COMMON_QPLL1FBDIV_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL1FBDIV_VAL (8'b00000000),
+ .GTHE4_COMMON_QPLL1LOCKDETCLK_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL1LOCKDETCLK_VAL (1'b0),
+ .GTHE4_COMMON_QPLL1LOCKEN_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL1LOCKEN_VAL (1'b1),
+ .GTHE4_COMMON_QPLL1PD_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL1PD_VAL (1'b0),
+ .GTHE4_COMMON_QPLL1REFCLKSEL_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL1REFCLKSEL_VAL (3'b001),
+ .GTHE4_COMMON_QPLL1RESET_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLL1RESET_VAL (1'b0),
+ .GTHE4_COMMON_QPLL1_CFG0 (16'b0011001100011100),
+ .GTHE4_COMMON_QPLL1_CFG1 (16'b1101000000111000),
+ .GTHE4_COMMON_QPLL1_CFG1_G3 (16'b1101000000111000),
+ .GTHE4_COMMON_QPLL1_CFG2 (16'b0000111111000011),
+ .GTHE4_COMMON_QPLL1_CFG2_G3 (16'b0000111111000011),
+ .GTHE4_COMMON_QPLL1_CFG3 (16'b0000000100100000),
+ .GTHE4_COMMON_QPLL1_CFG4 (16'b0000000000000011),
+ .GTHE4_COMMON_QPLL1_CP (10'b0011111111),
+ .GTHE4_COMMON_QPLL1_CP_G3 (10'b0001111111),
+ .GTHE4_COMMON_QPLL1_FBDIV (54),
+ .GTHE4_COMMON_QPLL1_FBDIV_G3 (80),
+ .GTHE4_COMMON_QPLL1_INIT_CFG0 (16'b0000001010110010),
+ .GTHE4_COMMON_QPLL1_INIT_CFG1 (8'b00000000),
+ .GTHE4_COMMON_QPLL1_LOCK_CFG (16'b0010010111101000),
+ .GTHE4_COMMON_QPLL1_LOCK_CFG_G3 (16'b0010010111101000),
+ .GTHE4_COMMON_QPLL1_LPF (10'b1000011111),
+ .GTHE4_COMMON_QPLL1_LPF_G3 (10'b0111010100),
+ .GTHE4_COMMON_QPLL1_PCI_EN (1'b0),
+ .GTHE4_COMMON_QPLL1_RATE_SW_USE_DRP (1'b1),
+ .GTHE4_COMMON_QPLL1_REFCLK_DIV (1),
+ .GTHE4_COMMON_QPLL1_SDM_CFG0 (16'b0000000000000000),
+ .GTHE4_COMMON_QPLL1_SDM_CFG1 (16'b0000000000000000),
+ .GTHE4_COMMON_QPLL1_SDM_CFG2 (16'b0000000000000000),
+ .GTHE4_COMMON_QPLLRSVD1_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLLRSVD1_VAL (8'b00000000),
+ .GTHE4_COMMON_QPLLRSVD2_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLLRSVD2_VAL (5'b00000),
+ .GTHE4_COMMON_QPLLRSVD3_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLLRSVD3_VAL (5'b00000),
+ .GTHE4_COMMON_QPLLRSVD4_TIE_EN (1'b0),
+ .GTHE4_COMMON_QPLLRSVD4_VAL (8'b00000000),
+ .GTHE4_COMMON_RCALENB_TIE_EN (1'b0),
+ .GTHE4_COMMON_RCALENB_VAL (1'b1),
+ .GTHE4_COMMON_RSVD_ATTR0 (16'b0000000000000000),
+ .GTHE4_COMMON_RSVD_ATTR1 (16'b0000000000000000),
+ .GTHE4_COMMON_RSVD_ATTR2 (16'b0000000000000000),
+ .GTHE4_COMMON_RSVD_ATTR3 (16'b0000000000000000),
+ .GTHE4_COMMON_RXRECCLKOUT0_SEL (2'b00),
+ .GTHE4_COMMON_RXRECCLKOUT1_SEL (2'b00),
+ .GTHE4_COMMON_SARC_ENB (1'b0),
+ .GTHE4_COMMON_SARC_SEL (1'b0),
+ .GTHE4_COMMON_SDM0DATA_TIE_EN (1'b0),
+ .GTHE4_COMMON_SDM0DATA_VAL (25'b0000000000000000000000000),
+ .GTHE4_COMMON_SDM0INITSEED0_0 (16'b0000000100010001),
+ .GTHE4_COMMON_SDM0INITSEED0_1 (9'b000010001),
+ .GTHE4_COMMON_SDM0RESET_TIE_EN (1'b0),
+ .GTHE4_COMMON_SDM0RESET_VAL (1'b0),
+ .GTHE4_COMMON_SDM0TOGGLE_TIE_EN (1'b0),
+ .GTHE4_COMMON_SDM0TOGGLE_VAL (1'b0),
+ .GTHE4_COMMON_SDM0WIDTH_TIE_EN (1'b0),
+ .GTHE4_COMMON_SDM0WIDTH_VAL (2'b00),
+ .GTHE4_COMMON_SDM1DATA_TIE_EN (1'b0),
+ .GTHE4_COMMON_SDM1DATA_VAL (25'b0010001011010000111001010),
+ .GTHE4_COMMON_SDM1INITSEED0_0 (16'b0000000100010001),
+ .GTHE4_COMMON_SDM1INITSEED0_1 (9'b000010001),
+ .GTHE4_COMMON_SDM1RESET_TIE_EN (1'b0),
+ .GTHE4_COMMON_SDM1RESET_VAL (1'b0),
+ .GTHE4_COMMON_SDM1TOGGLE_TIE_EN (1'b0),
+ .GTHE4_COMMON_SDM1TOGGLE_VAL (1'b0),
+ .GTHE4_COMMON_SDM1WIDTH_TIE_EN (1'b0),
+ .GTHE4_COMMON_SDM1WIDTH_VAL (2'b00),
+ .GTHE4_COMMON_SIM_DEVICE ("ULTRASCALE_PLUS"),
+ .GTHE4_COMMON_SIM_MODE ("FAST"),
+ .GTHE4_COMMON_SIM_RESET_SPEEDUP ("TRUE"),
+ .GTHE4_COMMON_TCONGPI_TIE_EN (1'b0),
+ .GTHE4_COMMON_TCONGPI_VAL (10'b0000000000),
+ .GTHE4_COMMON_TCONPOWERUP_TIE_EN (1'b0),
+ .GTHE4_COMMON_TCONPOWERUP_VAL (1'b0),
+ .GTHE4_COMMON_TCONRESET_TIE_EN (1'b0),
+ .GTHE4_COMMON_TCONRESET_VAL (2'b00),
+ .GTHE4_COMMON_TCONRSVDIN1_TIE_EN (1'b0),
+ .GTHE4_COMMON_TCONRSVDIN1_VAL (2'b00)
+) common_inst (
+
+ // inputs
+ .GTHE4_COMMON_BGBYPASSB (GTHE4_COMMON_BGBYPASSB),
+ .GTHE4_COMMON_BGMONITORENB (GTHE4_COMMON_BGMONITORENB),
+ .GTHE4_COMMON_BGPDB (GTHE4_COMMON_BGPDB),
+ .GTHE4_COMMON_BGRCALOVRD (GTHE4_COMMON_BGRCALOVRD),
+ .GTHE4_COMMON_BGRCALOVRDENB (GTHE4_COMMON_BGRCALOVRDENB),
+ .GTHE4_COMMON_DRPADDR (GTHE4_COMMON_DRPADDR),
+ .GTHE4_COMMON_DRPCLK (GTHE4_COMMON_DRPCLK),
+ .GTHE4_COMMON_DRPDI (GTHE4_COMMON_DRPDI),
+ .GTHE4_COMMON_DRPEN (GTHE4_COMMON_DRPEN),
+ .GTHE4_COMMON_DRPWE (GTHE4_COMMON_DRPWE),
+ .GTHE4_COMMON_GTGREFCLK0 (GTHE4_COMMON_GTGREFCLK0),
+ .GTHE4_COMMON_GTGREFCLK1 (GTHE4_COMMON_GTGREFCLK1),
+ .GTHE4_COMMON_GTNORTHREFCLK00 (GTHE4_COMMON_GTNORTHREFCLK00),
+ .GTHE4_COMMON_GTNORTHREFCLK01 (GTHE4_COMMON_GTNORTHREFCLK01),
+ .GTHE4_COMMON_GTNORTHREFCLK10 (GTHE4_COMMON_GTNORTHREFCLK10),
+ .GTHE4_COMMON_GTNORTHREFCLK11 (GTHE4_COMMON_GTNORTHREFCLK11),
+ .GTHE4_COMMON_GTREFCLK00 (GTHE4_COMMON_GTREFCLK00),
+ .GTHE4_COMMON_GTREFCLK01 (GTHE4_COMMON_GTREFCLK01),
+ .GTHE4_COMMON_GTREFCLK10 (GTHE4_COMMON_GTREFCLK10),
+ .GTHE4_COMMON_GTREFCLK11 (GTHE4_COMMON_GTREFCLK11),
+ .GTHE4_COMMON_GTSOUTHREFCLK00 (GTHE4_COMMON_GTSOUTHREFCLK00),
+ .GTHE4_COMMON_GTSOUTHREFCLK01 (GTHE4_COMMON_GTSOUTHREFCLK01),
+ .GTHE4_COMMON_GTSOUTHREFCLK10 (GTHE4_COMMON_GTSOUTHREFCLK10),
+ .GTHE4_COMMON_GTSOUTHREFCLK11 (GTHE4_COMMON_GTSOUTHREFCLK11),
+ .GTHE4_COMMON_PCIERATEQPLL0 (GTHE4_COMMON_PCIERATEQPLL0),
+ .GTHE4_COMMON_PCIERATEQPLL1 (GTHE4_COMMON_PCIERATEQPLL1),
+ .GTHE4_COMMON_PMARSVD0 (GTHE4_COMMON_PMARSVD0),
+ .GTHE4_COMMON_PMARSVD1 (GTHE4_COMMON_PMARSVD1),
+ .GTHE4_COMMON_QPLL0CLKRSVD0 (GTHE4_COMMON_QPLL0CLKRSVD0),
+ .GTHE4_COMMON_QPLL0CLKRSVD1 (GTHE4_COMMON_QPLL0CLKRSVD1),
+ .GTHE4_COMMON_QPLL0FBDIV (GTHE4_COMMON_QPLL0FBDIV),
+ .GTHE4_COMMON_QPLL0LOCKDETCLK (GTHE4_COMMON_QPLL0LOCKDETCLK),
+ .GTHE4_COMMON_QPLL0LOCKEN (GTHE4_COMMON_QPLL0LOCKEN),
+ .GTHE4_COMMON_QPLL0PD (GTHE4_COMMON_QPLL0PD),
+ .GTHE4_COMMON_QPLL0REFCLKSEL (GTHE4_COMMON_QPLL0REFCLKSEL),
+ .GTHE4_COMMON_QPLL0RESET (GTHE4_COMMON_QPLL0RESET),
+ .GTHE4_COMMON_QPLL1CLKRSVD0 (GTHE4_COMMON_QPLL1CLKRSVD0),
+ .GTHE4_COMMON_QPLL1CLKRSVD1 (GTHE4_COMMON_QPLL1CLKRSVD1),
+ .GTHE4_COMMON_QPLL1FBDIV (GTHE4_COMMON_QPLL1FBDIV),
+ .GTHE4_COMMON_QPLL1LOCKDETCLK (GTHE4_COMMON_QPLL1LOCKDETCLK),
+ .GTHE4_COMMON_QPLL1LOCKEN (GTHE4_COMMON_QPLL1LOCKEN),
+ .GTHE4_COMMON_QPLL1PD (GTHE4_COMMON_QPLL1PD),
+ .GTHE4_COMMON_QPLL1REFCLKSEL (GTHE4_COMMON_QPLL1REFCLKSEL),
+ .GTHE4_COMMON_QPLL1RESET (GTHE4_COMMON_QPLL1RESET),
+ .GTHE4_COMMON_QPLLRSVD1 (GTHE4_COMMON_QPLLRSVD1),
+ .GTHE4_COMMON_QPLLRSVD2 (GTHE4_COMMON_QPLLRSVD2),
+ .GTHE4_COMMON_QPLLRSVD3 (GTHE4_COMMON_QPLLRSVD3),
+ .GTHE4_COMMON_QPLLRSVD4 (GTHE4_COMMON_QPLLRSVD4),
+ .GTHE4_COMMON_RCALENB (GTHE4_COMMON_RCALENB),
+ .GTHE4_COMMON_SDM0DATA (GTHE4_COMMON_SDM0DATA),
+ .GTHE4_COMMON_SDM0RESET (GTHE4_COMMON_SDM0RESET),
+ .GTHE4_COMMON_SDM0TOGGLE (GTHE4_COMMON_SDM0TOGGLE),
+ .GTHE4_COMMON_SDM0WIDTH (GTHE4_COMMON_SDM0WIDTH),
+ .GTHE4_COMMON_SDM1DATA (GTHE4_COMMON_SDM1DATA),
+ .GTHE4_COMMON_SDM1RESET (GTHE4_COMMON_SDM1RESET),
+ .GTHE4_COMMON_SDM1TOGGLE (GTHE4_COMMON_SDM1TOGGLE),
+ .GTHE4_COMMON_SDM1WIDTH (GTHE4_COMMON_SDM1WIDTH),
+ .GTHE4_COMMON_TCONGPI (GTHE4_COMMON_TCONGPI),
+ .GTHE4_COMMON_TCONPOWERUP (GTHE4_COMMON_TCONPOWERUP),
+ .GTHE4_COMMON_TCONRESET (GTHE4_COMMON_TCONRESET),
+ .GTHE4_COMMON_TCONRSVDIN1 (GTHE4_COMMON_TCONRSVDIN1),
+
+ // outputs
+ .GTHE4_COMMON_DRPDO (GTHE4_COMMON_DRPDO),
+ .GTHE4_COMMON_DRPRDY (GTHE4_COMMON_DRPRDY),
+ .GTHE4_COMMON_PMARSVDOUT0 (GTHE4_COMMON_PMARSVDOUT0),
+ .GTHE4_COMMON_PMARSVDOUT1 (GTHE4_COMMON_PMARSVDOUT1),
+ .GTHE4_COMMON_QPLL0FBCLKLOST (GTHE4_COMMON_QPLL0FBCLKLOST),
+ .GTHE4_COMMON_QPLL0LOCK (GTHE4_COMMON_QPLL0LOCK),
+ .GTHE4_COMMON_QPLL0OUTCLK (GTHE4_COMMON_QPLL0OUTCLK),
+ .GTHE4_COMMON_QPLL0OUTREFCLK (GTHE4_COMMON_QPLL0OUTREFCLK),
+ .GTHE4_COMMON_QPLL0REFCLKLOST (GTHE4_COMMON_QPLL0REFCLKLOST),
+ .GTHE4_COMMON_QPLL1FBCLKLOST (GTHE4_COMMON_QPLL1FBCLKLOST),
+ .GTHE4_COMMON_QPLL1LOCK (GTHE4_COMMON_QPLL1LOCK),
+ .GTHE4_COMMON_QPLL1OUTCLK (GTHE4_COMMON_QPLL1OUTCLK),
+ .GTHE4_COMMON_QPLL1OUTREFCLK (GTHE4_COMMON_QPLL1OUTREFCLK),
+ .GTHE4_COMMON_QPLL1REFCLKLOST (GTHE4_COMMON_QPLL1REFCLKLOST),
+ .GTHE4_COMMON_QPLLDMONITOR0 (GTHE4_COMMON_QPLLDMONITOR0),
+ .GTHE4_COMMON_QPLLDMONITOR1 (GTHE4_COMMON_QPLLDMONITOR1),
+ .GTHE4_COMMON_REFCLKOUTMONITOR0 (GTHE4_COMMON_REFCLKOUTMONITOR0),
+ .GTHE4_COMMON_REFCLKOUTMONITOR1 (GTHE4_COMMON_REFCLKOUTMONITOR1),
+ .GTHE4_COMMON_RXRECCLK0SEL (GTHE4_COMMON_RXRECCLK0SEL),
+ .GTHE4_COMMON_RXRECCLK1SEL (GTHE4_COMMON_RXRECCLK1SEL),
+ .GTHE4_COMMON_SDM0FINALOUT (GTHE4_COMMON_SDM0FINALOUT),
+ .GTHE4_COMMON_SDM0TESTDATA (GTHE4_COMMON_SDM0TESTDATA),
+ .GTHE4_COMMON_SDM1FINALOUT (GTHE4_COMMON_SDM1FINALOUT),
+ .GTHE4_COMMON_SDM1TESTDATA (GTHE4_COMMON_SDM1TESTDATA),
+ .GTHE4_COMMON_TCONGPO (GTHE4_COMMON_TCONGPO),
+ .GTHE4_COMMON_TCONRSVDOUT0 (GTHE4_COMMON_TCONRSVDOUT0)
+);
+
+endmodule
+
diff --git a/hdl/combpm_gtwizard_gthe4_common_wrapper_inst.vhd b/hdl/combpm_gtwizard_gthe4_common_wrapper_inst.vhd
new file mode 100644
index 0000000000000000000000000000000000000000..15308220593b339fac584597822221f43619045a
--- /dev/null
+++ b/hdl/combpm_gtwizard_gthe4_common_wrapper_inst.vhd
@@ -0,0 +1,92 @@
+-- TRANSCEIVER COMMON BLOCK
+gthe4_common_wrapper_inst: entity work.combpm_gtwizard_gthe4_common_wrapper
+port map(
+ GTHE4_COMMON_BGBYPASSB => "1",
+ GTHE4_COMMON_BGMONITORENB => "1",
+ GTHE4_COMMON_BGPDB => "1",
+ GTHE4_COMMON_BGRCALOVRD => "11111",
+ GTHE4_COMMON_BGRCALOVRDENB => "1",
+ GTHE4_COMMON_DRPADDR => "0000000000000000",
+ GTHE4_COMMON_DRPCLK => "0",
+ GTHE4_COMMON_DRPDI => "0000000000000000",
+ GTHE4_COMMON_DRPEN => "0",
+ GTHE4_COMMON_DRPWE => "0",
+ GTHE4_COMMON_GTGREFCLK0 => "0",
+ GTHE4_COMMON_GTGREFCLK1 => "0",
+ GTHE4_COMMON_GTNORTHREFCLK00 => "0",
+ GTHE4_COMMON_GTNORTHREFCLK01 => "0",
+ GTHE4_COMMON_GTNORTHREFCLK10 => "0",
+ GTHE4_COMMON_GTNORTHREFCLK11 => "0",
+ GTHE4_COMMON_GTREFCLK00 => (gtrefclk00_int [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)]), // TODO
+ GTHE4_COMMON_GTREFCLK01 => (gtrefclk01_int [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)]), // TODO
+ GTHE4_COMMON_GTREFCLK10 => "0",
+ GTHE4_COMMON_GTREFCLK11 => "0",
+ GTHE4_COMMON_GTSOUTHREFCLK00 => "0",
+ GTHE4_COMMON_GTSOUTHREFCLK01 => "0",
+ GTHE4_COMMON_GTSOUTHREFCLK10 => "0",
+ GTHE4_COMMON_GTSOUTHREFCLK11 => "0",
+ GTHE4_COMMON_PCIERATEQPLL0 => "000",
+ GTHE4_COMMON_PCIERATEQPLL1 => "000",
+ GTHE4_COMMON_PMARSVD0 => "00000000",
+ GTHE4_COMMON_PMARSVD1 => "00000000",
+ GTHE4_COMMON_QPLL0CLKRSVD0 => "0",
+ GTHE4_COMMON_QPLL0CLKRSVD1 => "0",
+ GTHE4_COMMON_QPLL0FBDIV => "00000000",
+ GTHE4_COMMON_QPLL0LOCKDETCLK => "0",
+ GTHE4_COMMON_QPLL0LOCKEN => "1",
+ GTHE4_COMMON_QPLL0PD => "0",
+ GTHE4_COMMON_QPLL0REFCLKSEL => "001",
+ GTHE4_COMMON_QPLL0RESET => (qpll0reset_int [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)]), // TODO
+ GTHE4_COMMON_QPLL1CLKRSVD0 => "0",
+ GTHE4_COMMON_QPLL1CLKRSVD1 => "0",
+ GTHE4_COMMON_QPLL1FBDIV => "00000000",
+ GTHE4_COMMON_QPLL1LOCKDETCLK => "0",
+ GTHE4_COMMON_QPLL1LOCKEN => "1",
+ GTHE4_COMMON_QPLL1PD => "0",
+ GTHE4_COMMON_QPLL1REFCLKSEL => "001",
+ GTHE4_COMMON_QPLL1RESET => (qpll1reset_int [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)]), // TODO
+ GTHE4_COMMON_QPLLRSVD1 => "00000000",
+ GTHE4_COMMON_QPLLRSVD2 => "00000",
+ GTHE4_COMMON_QPLLRSVD3 => "00000",
+ GTHE4_COMMON_QPLLRSVD4 => "00000000",
+ GTHE4_COMMON_RCALENB => "1",
+ GTHE4_COMMON_SDM0DATA => "0000000000000000000000000",
+ GTHE4_COMMON_SDM0RESET => "0",
+ GTHE4_COMMON_SDM0TOGGLE => "0",
+ GTHE4_COMMON_SDM0WIDTH => "00",
+ GTHE4_COMMON_SDM1DATA => "0010001011010000111001010",
+ GTHE4_COMMON_SDM1RESET => "0",
+ GTHE4_COMMON_SDM1TOGGLE => "0",
+ GTHE4_COMMON_SDM1WIDTH => "00",
+ GTHE4_COMMON_TCONGPI => "0000000000",
+ GTHE4_COMMON_TCONPOWERUP => "0",
+ GTHE4_COMMON_TCONRESET => "00",
+ GTHE4_COMMON_TCONRSVDIN1 => "00",
+ GTHE4_COMMON_DRPDO => open,
+ GTHE4_COMMON_DRPRDY => open,
+ GTHE4_COMMON_PMARSVDOUT0 => open,
+ GTHE4_COMMON_PMARSVDOUT1 => open,
+ GTHE4_COMMON_QPLL0FBCLKLOST => open,
+ GTHE4_COMMON_QPLL0LOCK => (qpll0lock_int [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)]), // TODO
+ GTHE4_COMMON_QPLL0OUTCLK => (qpll0outclk_out [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)]), // TODO
+ GTHE4_COMMON_QPLL0OUTREFCLK => (qpll0outrefclk_out [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)]), // TODO open
+ GTHE4_COMMON_QPLL0REFCLKLOST => open,
+ GTHE4_COMMON_QPLL1FBCLKLOST => open,
+ GTHE4_COMMON_QPLL1LOCK => (qpll1lock_int [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)]), // TODO
+ GTHE4_COMMON_QPLL1OUTCLK => (qpll1outclk_out [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)]), // TODO
+ GTHE4_COMMON_QPLL1OUTREFCLK => (qpll1outrefclk_out [f_ub_cm( 1,(4*cm)+3) : f_lb_cm( 1,4*cm)]), // TODO open
+ GTHE4_COMMON_QPLL1REFCLKLOST => open,
+ GTHE4_COMMON_QPLLDMONITOR0 => open,
+ GTHE4_COMMON_QPLLDMONITOR1 => open,
+ GTHE4_COMMON_REFCLKOUTMONITOR0 => open,
+ GTHE4_COMMON_REFCLKOUTMONITOR1 => open,
+ GTHE4_COMMON_RXRECCLK0SEL => open,
+ GTHE4_COMMON_RXRECCLK1SEL => open,
+ GTHE4_COMMON_SDM0FINALOUT => open,
+ GTHE4_COMMON_SDM0TESTDATA => open,
+ GTHE4_COMMON_SDM1FINALOUT => open,
+ GTHE4_COMMON_SDM1TESTDATA => open,
+ GTHE4_COMMON_TCONGPO => open,
+ GTHE4_COMMON_TCONRSVDOUT0 => open
+);
+
diff --git a/hdl/combpm_gtwrapper.vhd b/hdl/combpm_gtwrapper.vhd
deleted file mode 100644
index 4658bb872399c0f22421e55fbffa78769ee20be6..0000000000000000000000000000000000000000
--- a/hdl/combpm_gtwrapper.vhd
+++ /dev/null
@@ -1,183 +0,0 @@
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_misc.all;
-
-library UNISIM;
-use UNISIM.vcomponents.all;
-
-use work.combpm_gtwrapper_pkg.all;
-
-entity combpm_gtwrapper is
- port(
- -- 100MHz clock, main ref clock
- clk_100 : in std_logic;
-
- -- Usrclock for data transfer
- usrclk : out std_logic;
-
- -- Async reset active low
- rst_n : in std_logic;
-
- -- Differential reference clock inputs and buffered output
- mgtrefclk_p : in std_logic;
- mgtrefclk_n : in std_logic;
- mgtrefclk : out std_logic;
-
- -- SFP interfaces
- sfp_txp : out std_logic_vector(C_NUM_CHAN-1 downto 0);
- sfp_txn : out std_logic_vector(C_NUM_CHAN-1 downto 0);
- sfp_rxp : in std_logic_vector(C_NUM_CHAN-1 downto 0);
- sfp_rxn : in std_logic_vector(C_NUM_CHAN-1 downto 0);
- sfp_rx_los : in std_logic_vector(C_NUM_CHAN-1 downto 0);
- sfp_mod_abs : in std_logic_vector(C_NUM_CHAN-1 downto 0);
- sfp_tx_disable : out std_logic_vector(C_NUM_CHAN-1 downto 0);
- sfp_tx_fault : in std_logic_vector(C_NUM_CHAN-1 downto 0);
-
- -- GT interfaces
- gt_datarx : out std_logic_vector(16*C_NUM_CHAN-1 downto 0);
- gt_datatx : in std_logic_vector(16*C_NUM_CHAN-1 downto 0);
- gt_powergood : out std_logic_vector(C_NUM_CHAN-1 downto 0);
- gt_qplllock : out std_logic_vector(C_NUM_CHAN-1 downto 0);
- gt_txclkactive : out std_logic_vector(C_NUM_CHAN-1 downto 0);
- gt_rxclkactive : out std_logic_vector(C_NUM_CHAN-1 downto 0);
- gt_txresetdone : out std_logic_vector(C_NUM_CHAN-1 downto 0);
- gt_rxresetdone : out std_logic_vector(C_NUM_CHAN-1 downto 0);
- gt_rxbyteisaligned : out std_logic_vector(C_NUM_CHAN-1 downto 0);
- gt_rxbyterealign : out std_logic_vector(C_NUM_CHAN-1 downto 0);
- gt_rxcommadet : out std_logic_vector(C_NUM_CHAN-1 downto 0);
- gt_rxcdrlock : out std_logic_vector(C_NUM_CHAN-1 downto 0);
- gt_txfault : out std_logic_vector(C_NUM_CHAN-1 downto 0);
- gt_rxlos : out std_logic_vector(C_NUM_CHAN-1 downto 0);
- gt_modabs : out std_logic_vector(C_NUM_CHAN-1 downto 0);
- gt_rstall : in std_logic_vector(C_NUM_CHAN-1 downto 0);
- gt_rxcommadeten : in std_logic_vector(C_NUM_CHAN-1 downto 0);
- gt_txdisable : in std_logic_vector(C_NUM_CHAN-1 downto 0)
- );
-end entity combpm_gtwrapper;
-
-architecture struct of combpm_gtwrapper is
-
- --------------------------------
- -- INTERFACE PORT ASSOCIATION --
- --------------------------------
- ATTRIBUTE X_INTERFACE_INFO : STRING;
- ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
-
- ATTRIBUTE X_INTERFACE_INFO of clk_100 : SIGNAL is "xilinx.com:signal:clock:1.0 clk_100 CLK";
- ATTRIBUTE X_INTERFACE_PARAMETER of clk_100 : SIGNAL is "FREQ 100000000";
- ATTRIBUTE X_INTERFACE_INFO of rst_n : SIGNAL is "xilinx.com:signal:reset:1.0 rst_n RST";
- ATTRIBUTE X_INTERFACE_PARAMETER of rst_n : SIGNAL is "POLARITY ACTIVE_LOW";
-
- ------------------------
- -- SIGNAL DECLARATION --
- ------------------------
- signal txclkactive : std_logic;
- signal rxclkactive : std_logic;
- signal rstall : std_logic;
- signal txresetdone : std_logic;
- signal rxresetdone : std_logic;
- signal qplllock : std_logic;
- signal ref_clk : std_logic;
-
-
-begin
-
- ---------------------
- -- DIFF CLK BUFFER --
- ---------------------
- ibufd_clkref_inst: IBUFDS_GTE4
- generic map (
- REFCLK_EN_TX_PATH => '0',
- REFCLK_HROW_CK_SEL => "00",
- REFCLK_ICNTL_RX => "00"
- )
- port map (
- O => ref_clk,
- ODIV2 => open,
- CEB => '0',
- I => mgtrefclk_p,
- IB => mgtrefclk_n
- );
- -- Connect to output port
- mgtrefclk <= ref_clk;
-
-
- -----------------
- -- MAP SIGNALS --
- -----------------
- g_map_sigs:for I in 0 to C_NUM_CHAN-1 generate
- gt_txclkactive(I) <= txclkactive;
- gt_rxclkactive(I) <= rxclkactive;
- gt_txresetdone(I) <= txresetdone;
- gt_rxresetdone(I) <= rxresetdone;
- gt_qplllock(I) <= qplllock;
- end generate g_map_sigs;
-
- rstall <= or_reduce(gt_rstall);
- gt_txfault <= sfp_tx_fault;
- gt_rxlos <= sfp_rx_los;
- gt_modabs <= sfp_mod_abs;
- sfp_tx_disable <= gt_txdisable;
-
- -- Temporary
- qplllock <= '1';
-
- --------------------------
- -- TRANSCEIVER INSTANCE --
- --------------------------
- gtwiz_inst: combpm_gtwizard
- PORT MAP (
- gtwiz_userclk_tx_reset_in => "0",
- gtwiz_userclk_tx_srcclk_out => open,
- gtwiz_userclk_tx_usrclk_out => open,
- gtwiz_userclk_tx_usrclk2_out => open,
- gtwiz_userclk_tx_active_out(0) => txclkactive,
- gtwiz_userclk_rx_reset_in => "0",
- gtwiz_userclk_rx_srcclk_out => open,
- gtwiz_userclk_rx_usrclk_out(0) => usrclk,
- gtwiz_userclk_rx_usrclk2_out => open,
- gtwiz_userclk_rx_active_out(0) => rxclkactive,
- gtwiz_reset_clk_freerun_in(0) => clk_100,
- gtwiz_reset_all_in(0) => rstall,
- gtwiz_reset_tx_pll_and_datapath_in => "0",
- gtwiz_reset_tx_datapath_in => "0",
- gtwiz_reset_rx_pll_and_datapath_in => "0",
- gtwiz_reset_rx_datapath_in => "0",
- gtwiz_reset_rx_cdr_stable_out => open,
- gtwiz_reset_tx_done_out(0) => txresetdone,
- gtwiz_reset_rx_done_out(0) => rxresetdone,
- gtwiz_userdata_tx_in => gt_datatx,
- gtwiz_userdata_rx_out => gt_datarx,
- gtrefclk01_in(0) => ref_clk,
- --qpll1lock_out(0) => qplllock,
- qpll1outclk_out => open,
- qpll1outrefclk_out => open,
- gthrxn_in => sfp_rxn,
- gthrxp_in => sfp_rxp,
- rxbufreset_in => (others => '0'),
- rx8b10ben_in => (others => '1'),
- rxcommadeten_in => gt_rxcommadeten,
- rxmcommaalignen_in => (others => '1'),
- rxpcommaalignen_in => (others => '1'),
- tx8b10ben_in => (others => '1'),
- txctrl0_in => (others => '0'),
- txctrl1_in => (others => '0'),
- txctrl2_in => (others => '0'),
- gthtxn_out => sfp_txn,
- gthtxp_out => sfp_txp,
- gtpowergood_out => gt_powergood,
- rxbufstatus_out => open,
- rxbyteisaligned_out => gt_rxbyteisaligned,
- rxbyterealign_out => gt_rxbyterealign,
- rxclkcorcnt_out => open,
- rxcommadet_out => gt_rxcommadet,
- rxctrl0_out => open,
- rxctrl1_out => open,
- rxctrl2_out => open,
- rxctrl3_out => open,
- rxpmaresetdone_out => open,
- txpmaresetdone_out => open
- );
-
-end architecture struct;
-
diff --git a/hdl/gtwizard_ultrascale_v1_7_gthe4_common.v b/hdl/gtwizard_ultrascale_v1_7_gthe4_common.v
new file mode 100755
index 0000000000000000000000000000000000000000..3f7c77b6785fdfb4b93f54784175b0d5ad66af9e
--- /dev/null
+++ b/hdl/gtwizard_ultrascale_v1_7_gthe4_common.v
@@ -0,0 +1,928 @@
+//------------------------------------------------------------------------------
+// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
+//
+// This file contains confidential and proprietary information
+// of Xilinx, Inc. and is protected under U.S. and
+// international copyright and other intellectual property
+// laws.
+//
+// DISCLAIMER
+// This disclaimer is not a license and does not grant any
+// rights to the materials distributed herewith. Except as
+// otherwise provided in a valid license issued to you by
+// Xilinx, and to the maximum extent permitted by applicable
+// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
+// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
+// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
+// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
+// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
+// (2) Xilinx shall not be liable (whether in contract or tort,
+// including negligence, or under any other theory of
+// liability) for any loss or damage of any kind or nature
+// related to, arising under or in connection with these
+// materials, including for any direct, or any indirect,
+// special, incidental, or consequential loss or damage
+// (including loss of data, profits, goodwill, or any type of
+// loss or damage suffered as a result of any action brought
+// by a third party) even if such damage or loss was
+// reasonably foreseeable or Xilinx had been advised of the
+// possibility of the same.
+//
+// CRITICAL APPLICATIONS
+// Xilinx products are not designed or intended to be fail-
+// safe, or for use in any application requiring fail-safe
+// performance, such as life-support or safety devices or
+// systems, Class III medical devices, nuclear facilities,
+// applications related to the deployment of airbags, or any
+// other applications that could lead to death, personal
+// injury, or severe property or environmental damage
+// (individually and collectively, "Critical
+// Applications"). Customer assumes the sole risk and
+// liability of any use of Xilinx products in Critical
+// Applications, subject only to applicable laws and
+// regulations governing limitations on product liability.
+//
+// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
+// PART OF THIS FILE AT ALL TIMES.
+//------------------------------------------------------------------------------
+
+// ***************************
+// * DO NOT MODIFY THIS FILE *
+// ***************************
+
+`timescale 1ps/1ps
+
+module gtwizard_ultrascale_v1_7_9_gthe4_common #(
+
+
+ // -------------------------------------------------------------------------------------------------------------------
+ // Parameters relating to GTHE4_COMMON primitive
+ // -------------------------------------------------------------------------------------------------------------------
+
+ // primitive wrapper parameters which override corresponding GTHE4_COMMON primitive parameters
+ parameter [0:0] GTHE4_COMMON_AEN_QPLL0_FBDIV = 1'b1,
+ parameter [0:0] GTHE4_COMMON_AEN_QPLL1_FBDIV = 1'b1,
+ parameter [0:0] GTHE4_COMMON_AEN_SDM0TOGGLE = 1'b0,
+ parameter [0:0] GTHE4_COMMON_AEN_SDM1TOGGLE = 1'b0,
+ parameter [0:0] GTHE4_COMMON_A_SDM0TOGGLE = 1'b0,
+ parameter [8:0] GTHE4_COMMON_A_SDM1DATA_HIGH = 9'b000000000,
+ parameter [15:0] GTHE4_COMMON_A_SDM1DATA_LOW = 16'b0000000000000000,
+ parameter [0:0] GTHE4_COMMON_A_SDM1TOGGLE = 1'b0,
+ parameter [15:0] GTHE4_COMMON_BIAS_CFG0 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_BIAS_CFG1 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_BIAS_CFG2 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_BIAS_CFG3 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_BIAS_CFG4 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_BIAS_CFG_RSVD = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_COMMON_CFG0 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_COMMON_CFG1 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_POR_CFG = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_PPF0_CFG = 16'h0F00,
+ parameter [15:0] GTHE4_COMMON_PPF1_CFG = 16'h0F00,
+ parameter GTHE4_COMMON_QPLL0CLKOUT_RATE = "FULL",
+ parameter [15:0] GTHE4_COMMON_QPLL0_CFG0 = 16'h391C,
+ parameter [15:0] GTHE4_COMMON_QPLL0_CFG1 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_QPLL0_CFG1_G3 = 16'h0020,
+ parameter [15:0] GTHE4_COMMON_QPLL0_CFG2 = 16'h0F80,
+ parameter [15:0] GTHE4_COMMON_QPLL0_CFG2_G3 = 16'h0F80,
+ parameter [15:0] GTHE4_COMMON_QPLL0_CFG3 = 16'h0120,
+ parameter [15:0] GTHE4_COMMON_QPLL0_CFG4 = 16'h0002,
+ parameter [9:0] GTHE4_COMMON_QPLL0_CP = 10'b0000011111,
+ parameter [9:0] GTHE4_COMMON_QPLL0_CP_G3 = 10'b0000011111,
+ parameter integer GTHE4_COMMON_QPLL0_FBDIV = 66,
+ parameter integer GTHE4_COMMON_QPLL0_FBDIV_G3 = 80,
+ parameter [15:0] GTHE4_COMMON_QPLL0_INIT_CFG0 = 16'h0000,
+ parameter [7:0] GTHE4_COMMON_QPLL0_INIT_CFG1 = 8'h00,
+ parameter [15:0] GTHE4_COMMON_QPLL0_LOCK_CFG = 16'h01E8,
+ parameter [15:0] GTHE4_COMMON_QPLL0_LOCK_CFG_G3 = 16'h21E8,
+ parameter [9:0] GTHE4_COMMON_QPLL0_LPF = 10'b1011111111,
+ parameter [9:0] GTHE4_COMMON_QPLL0_LPF_G3 = 10'b1111111111,
+ parameter [0:0] GTHE4_COMMON_QPLL0_PCI_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0_RATE_SW_USE_DRP = 1'b0,
+ parameter integer GTHE4_COMMON_QPLL0_REFCLK_DIV = 1,
+ parameter [15:0] GTHE4_COMMON_QPLL0_SDM_CFG0 = 16'h0040,
+ parameter [15:0] GTHE4_COMMON_QPLL0_SDM_CFG1 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_QPLL0_SDM_CFG2 = 16'h0000,
+ parameter GTHE4_COMMON_QPLL1CLKOUT_RATE = "FULL",
+ parameter [15:0] GTHE4_COMMON_QPLL1_CFG0 = 16'h691C,
+ parameter [15:0] GTHE4_COMMON_QPLL1_CFG1 = 16'h0020,
+ parameter [15:0] GTHE4_COMMON_QPLL1_CFG1_G3 = 16'h0020,
+ parameter [15:0] GTHE4_COMMON_QPLL1_CFG2 = 16'h0F80,
+ parameter [15:0] GTHE4_COMMON_QPLL1_CFG2_G3 = 16'h0F80,
+ parameter [15:0] GTHE4_COMMON_QPLL1_CFG3 = 16'h0120,
+ parameter [15:0] GTHE4_COMMON_QPLL1_CFG4 = 16'h0002,
+ parameter [9:0] GTHE4_COMMON_QPLL1_CP = 10'b0000011111,
+ parameter [9:0] GTHE4_COMMON_QPLL1_CP_G3 = 10'b0000011111,
+ parameter integer GTHE4_COMMON_QPLL1_FBDIV = 66,
+ parameter integer GTHE4_COMMON_QPLL1_FBDIV_G3 = 80,
+ parameter [15:0] GTHE4_COMMON_QPLL1_INIT_CFG0 = 16'h0000,
+ parameter [7:0] GTHE4_COMMON_QPLL1_INIT_CFG1 = 8'h00,
+ parameter [15:0] GTHE4_COMMON_QPLL1_LOCK_CFG = 16'h01E8,
+ parameter [15:0] GTHE4_COMMON_QPLL1_LOCK_CFG_G3 = 16'h21E8,
+ parameter [9:0] GTHE4_COMMON_QPLL1_LPF = 10'b1011111111,
+ parameter [9:0] GTHE4_COMMON_QPLL1_LPF_G3 = 10'b1111111111,
+ parameter [0:0] GTHE4_COMMON_QPLL1_PCI_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1_RATE_SW_USE_DRP = 1'b0,
+ parameter integer GTHE4_COMMON_QPLL1_REFCLK_DIV = 1,
+ parameter [15:0] GTHE4_COMMON_QPLL1_SDM_CFG0 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_QPLL1_SDM_CFG1 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_QPLL1_SDM_CFG2 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_RSVD_ATTR0 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_RSVD_ATTR1 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_RSVD_ATTR2 = 16'h0000,
+ parameter [15:0] GTHE4_COMMON_RSVD_ATTR3 = 16'h0000,
+ parameter [1:0] GTHE4_COMMON_RXRECCLKOUT0_SEL = 2'b00,
+ parameter [1:0] GTHE4_COMMON_RXRECCLKOUT1_SEL = 2'b00,
+ parameter [0:0] GTHE4_COMMON_SARC_ENB = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SARC_SEL = 1'b0,
+ parameter [15:0] GTHE4_COMMON_SDM0INITSEED0_0 = 16'b0000000000000000,
+ parameter [8:0] GTHE4_COMMON_SDM0INITSEED0_1 = 9'b000000000,
+ parameter [15:0] GTHE4_COMMON_SDM1INITSEED0_0 = 16'b0000000000000000,
+ parameter [8:0] GTHE4_COMMON_SDM1INITSEED0_1 = 9'b000000000,
+ parameter GTHE4_COMMON_SIM_MODE = "FAST",
+ parameter GTHE4_COMMON_SIM_RESET_SPEEDUP = "TRUE",
+ parameter GTHE4_COMMON_SIM_DEVICE = "ULTRASCALE_PLUS",
+
+ // primitive wrapper parameters which specify GTHE4_COMMON primitive input port default driver values
+ parameter [0:0] GTHE4_COMMON_BGBYPASSB_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_BGMONITORENB_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_BGPDB_VAL = 1'b0,
+ parameter [4:0] GTHE4_COMMON_BGRCALOVRD_VAL = 5'b0,
+ parameter [0:0] GTHE4_COMMON_BGRCALOVRDENB_VAL = 1'b0,
+ parameter [15:0] GTHE4_COMMON_DRPADDR_VAL = 16'b0,
+ parameter [0:0] GTHE4_COMMON_DRPCLK_VAL = 1'b0,
+ parameter [15:0] GTHE4_COMMON_DRPDI_VAL = 16'b0,
+ parameter [0:0] GTHE4_COMMON_DRPEN_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_DRPWE_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTGREFCLK0_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTGREFCLK1_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTNORTHREFCLK00_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTNORTHREFCLK01_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTNORTHREFCLK10_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTNORTHREFCLK11_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTREFCLK00_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTREFCLK01_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTREFCLK10_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTREFCLK11_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTSOUTHREFCLK00_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTSOUTHREFCLK01_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTSOUTHREFCLK10_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTSOUTHREFCLK11_VAL = 1'b0,
+ parameter [2:0] GTHE4_COMMON_PCIERATEQPLL0_VAL = 3'b0,
+ parameter [2:0] GTHE4_COMMON_PCIERATEQPLL1_VAL = 3'b0,
+ parameter [7:0] GTHE4_COMMON_PMARSVD0_VAL = 8'b0,
+ parameter [7:0] GTHE4_COMMON_PMARSVD1_VAL = 8'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0CLKRSVD0_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0CLKRSVD1_VAL = 1'b0,
+ parameter [7:0] GTHE4_COMMON_QPLL0FBDIV_VAL = 8'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0LOCKDETCLK_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0LOCKEN_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0PD_VAL = 1'b0,
+ parameter [2:0] GTHE4_COMMON_QPLL0REFCLKSEL_VAL = 3'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0RESET_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1CLKRSVD0_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1CLKRSVD1_VAL = 1'b0,
+ parameter [7:0] GTHE4_COMMON_QPLL1FBDIV_VAL = 8'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1LOCKDETCLK_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1LOCKEN_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1PD_VAL = 1'b0,
+ parameter [2:0] GTHE4_COMMON_QPLL1REFCLKSEL_VAL = 3'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1RESET_VAL = 1'b0,
+ parameter [7:0] GTHE4_COMMON_QPLLRSVD1_VAL = 8'b0,
+ parameter [4:0] GTHE4_COMMON_QPLLRSVD2_VAL = 5'b0,
+ parameter [4:0] GTHE4_COMMON_QPLLRSVD3_VAL = 5'b0,
+ parameter [7:0] GTHE4_COMMON_QPLLRSVD4_VAL = 8'b0,
+ parameter [0:0] GTHE4_COMMON_RCALENB_VAL = 1'b0,
+ parameter [24:0] GTHE4_COMMON_SDM0DATA_VAL = 25'b0,
+ parameter [0:0] GTHE4_COMMON_SDM0RESET_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM0TOGGLE_VAL = 1'b0,
+ parameter [1:0] GTHE4_COMMON_SDM0WIDTH_VAL = 2'b0,
+ parameter [24:0] GTHE4_COMMON_SDM1DATA_VAL = 25'b0,
+ parameter [0:0] GTHE4_COMMON_SDM1RESET_VAL = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM1TOGGLE_VAL = 1'b0,
+ parameter [1:0] GTHE4_COMMON_SDM1WIDTH_VAL = 2'b0,
+ parameter [9:0] GTHE4_COMMON_TCONGPI_VAL = 10'b0,
+ parameter [0:0] GTHE4_COMMON_TCONPOWERUP_VAL = 1'b0,
+ parameter [1:0] GTHE4_COMMON_TCONRESET_VAL = 2'b0,
+ parameter [1:0] GTHE4_COMMON_TCONRSVDIN1_VAL = 2'b0,
+
+ // primitive wrapper parameters which control GTHE4_COMMON primitive input port tie-off enablement
+ parameter [0:0] GTHE4_COMMON_BGBYPASSB_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_BGMONITORENB_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_BGPDB_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_BGRCALOVRD_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_BGRCALOVRDENB_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_DRPADDR_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_DRPCLK_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_DRPDI_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_DRPEN_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_DRPWE_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTGREFCLK0_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTGREFCLK1_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTNORTHREFCLK00_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTNORTHREFCLK01_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTNORTHREFCLK10_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTNORTHREFCLK11_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTREFCLK00_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTREFCLK01_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTREFCLK10_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTREFCLK11_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTSOUTHREFCLK00_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTSOUTHREFCLK01_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTSOUTHREFCLK10_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_GTSOUTHREFCLK11_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_PCIERATEQPLL0_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_PCIERATEQPLL1_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_PMARSVD0_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_PMARSVD1_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0CLKRSVD0_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0CLKRSVD1_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0FBDIV_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0LOCKDETCLK_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0LOCKEN_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0PD_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0REFCLKSEL_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL0RESET_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1CLKRSVD0_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1CLKRSVD1_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1FBDIV_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1LOCKDETCLK_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1LOCKEN_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1PD_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1REFCLKSEL_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLL1RESET_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLLRSVD1_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLLRSVD2_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLLRSVD3_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_QPLLRSVD4_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_RCALENB_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM0DATA_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM0RESET_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM0TOGGLE_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM0WIDTH_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM1DATA_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM1RESET_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM1TOGGLE_TIE_EN = 1'b0,
+ parameter [0:0] GTHE4_COMMON_SDM1WIDTH_TIE_EN = 1'b0,
+ parameter [9:0] GTHE4_COMMON_TCONGPI_TIE_EN = 10'b0,
+ parameter [0:0] GTHE4_COMMON_TCONPOWERUP_TIE_EN = 1'b0,
+ parameter [1:0] GTHE4_COMMON_TCONRESET_TIE_EN = 2'b0,
+ parameter [1:0] GTHE4_COMMON_TCONRSVDIN1_TIE_EN = 2'b0
+
+)(
+
+
+ // -------------------------------------------------------------------------------------------------------------------
+ // Ports relating to GTHE4_COMMON primitive
+ // -------------------------------------------------------------------------------------------------------------------
+
+ // primitive wrapper input ports which can drive corresponding GTHE4_COMMON primitive input ports
+ input wire [ 0:0] GTHE4_COMMON_BGBYPASSB,
+ input wire [ 0:0] GTHE4_COMMON_BGMONITORENB,
+ input wire [ 0:0] GTHE4_COMMON_BGPDB,
+ input wire [ 4:0] GTHE4_COMMON_BGRCALOVRD,
+ input wire [ 0:0] GTHE4_COMMON_BGRCALOVRDENB,
+ input wire [15:0] GTHE4_COMMON_DRPADDR,
+ input wire [ 0:0] GTHE4_COMMON_DRPCLK,
+ input wire [15:0] GTHE4_COMMON_DRPDI,
+ input wire [ 0:0] GTHE4_COMMON_DRPEN,
+ input wire [ 0:0] GTHE4_COMMON_DRPWE,
+ input wire [ 0:0] GTHE4_COMMON_GTGREFCLK0,
+ input wire [ 0:0] GTHE4_COMMON_GTGREFCLK1,
+ input wire [ 0:0] GTHE4_COMMON_GTNORTHREFCLK00,
+ input wire [ 0:0] GTHE4_COMMON_GTNORTHREFCLK01,
+ input wire [ 0:0] GTHE4_COMMON_GTNORTHREFCLK10,
+ input wire [ 0:0] GTHE4_COMMON_GTNORTHREFCLK11,
+ input wire [ 0:0] GTHE4_COMMON_GTREFCLK00,
+ input wire [ 0:0] GTHE4_COMMON_GTREFCLK01,
+ input wire [ 0:0] GTHE4_COMMON_GTREFCLK10,
+ input wire [ 0:0] GTHE4_COMMON_GTREFCLK11,
+ input wire [ 0:0] GTHE4_COMMON_GTSOUTHREFCLK00,
+ input wire [ 0:0] GTHE4_COMMON_GTSOUTHREFCLK01,
+ input wire [ 0:0] GTHE4_COMMON_GTSOUTHREFCLK10,
+ input wire [ 0:0] GTHE4_COMMON_GTSOUTHREFCLK11,
+ input wire [ 2:0] GTHE4_COMMON_PCIERATEQPLL0,
+ input wire [ 2:0] GTHE4_COMMON_PCIERATEQPLL1,
+ input wire [ 7:0] GTHE4_COMMON_PMARSVD0,
+ input wire [ 7:0] GTHE4_COMMON_PMARSVD1,
+ input wire [ 0:0] GTHE4_COMMON_QPLL0CLKRSVD0,
+ input wire [ 0:0] GTHE4_COMMON_QPLL0CLKRSVD1,
+ input wire [ 7:0] GTHE4_COMMON_QPLL0FBDIV,
+ input wire [ 0:0] GTHE4_COMMON_QPLL0LOCKDETCLK,
+ input wire [ 0:0] GTHE4_COMMON_QPLL0LOCKEN,
+ input wire [ 0:0] GTHE4_COMMON_QPLL0PD,
+ input wire [ 2:0] GTHE4_COMMON_QPLL0REFCLKSEL,
+ input wire [ 0:0] GTHE4_COMMON_QPLL0RESET,
+ input wire [ 0:0] GTHE4_COMMON_QPLL1CLKRSVD0,
+ input wire [ 0:0] GTHE4_COMMON_QPLL1CLKRSVD1,
+ input wire [ 7:0] GTHE4_COMMON_QPLL1FBDIV,
+ input wire [ 0:0] GTHE4_COMMON_QPLL1LOCKDETCLK,
+ input wire [ 0:0] GTHE4_COMMON_QPLL1LOCKEN,
+ input wire [ 0:0] GTHE4_COMMON_QPLL1PD,
+ input wire [ 2:0] GTHE4_COMMON_QPLL1REFCLKSEL,
+ input wire [ 0:0] GTHE4_COMMON_QPLL1RESET,
+ input wire [ 7:0] GTHE4_COMMON_QPLLRSVD1,
+ input wire [ 4:0] GTHE4_COMMON_QPLLRSVD2,
+ input wire [ 4:0] GTHE4_COMMON_QPLLRSVD3,
+ input wire [ 7:0] GTHE4_COMMON_QPLLRSVD4,
+ input wire [ 0:0] GTHE4_COMMON_RCALENB,
+ input wire [24:0] GTHE4_COMMON_SDM0DATA,
+ input wire [ 0:0] GTHE4_COMMON_SDM0RESET,
+ input wire [ 0:0] GTHE4_COMMON_SDM0TOGGLE,
+ input wire [ 1:0] GTHE4_COMMON_SDM0WIDTH,
+ input wire [24:0] GTHE4_COMMON_SDM1DATA,
+ input wire [ 0:0] GTHE4_COMMON_SDM1RESET,
+ input wire [ 0:0] GTHE4_COMMON_SDM1TOGGLE,
+ input wire [ 1:0] GTHE4_COMMON_SDM1WIDTH,
+ input wire [ 9:0] GTHE4_COMMON_TCONGPI,
+ input wire [ 0:0] GTHE4_COMMON_TCONPOWERUP,
+ input wire [ 1:0] GTHE4_COMMON_TCONRESET,
+ input wire [ 1:0] GTHE4_COMMON_TCONRSVDIN1,
+
+ // primitive wrapper output ports which are driven by corresponding GTHE4_COMMON primitive output ports
+ output wire [15:0] GTHE4_COMMON_DRPDO,
+ output wire [ 0:0] GTHE4_COMMON_DRPRDY,
+ output wire [ 7:0] GTHE4_COMMON_PMARSVDOUT0,
+ output wire [ 7:0] GTHE4_COMMON_PMARSVDOUT1,
+ output wire [ 0:0] GTHE4_COMMON_QPLL0FBCLKLOST,
+ output wire [ 0:0] GTHE4_COMMON_QPLL0LOCK,
+ output wire [ 0:0] GTHE4_COMMON_QPLL0OUTCLK,
+ output wire [ 0:0] GTHE4_COMMON_QPLL0OUTREFCLK,
+ output wire [ 0:0] GTHE4_COMMON_QPLL0REFCLKLOST,
+ output wire [ 0:0] GTHE4_COMMON_QPLL1FBCLKLOST,
+ output wire [ 0:0] GTHE4_COMMON_QPLL1LOCK,
+ output wire [ 0:0] GTHE4_COMMON_QPLL1OUTCLK,
+ output wire [ 0:0] GTHE4_COMMON_QPLL1OUTREFCLK,
+ output wire [ 0:0] GTHE4_COMMON_QPLL1REFCLKLOST,
+ output wire [ 7:0] GTHE4_COMMON_QPLLDMONITOR0,
+ output wire [ 7:0] GTHE4_COMMON_QPLLDMONITOR1,
+ output wire [ 0:0] GTHE4_COMMON_REFCLKOUTMONITOR0,
+ output wire [ 0:0] GTHE4_COMMON_REFCLKOUTMONITOR1,
+ output wire [ 1:0] GTHE4_COMMON_RXRECCLK0SEL,
+ output wire [ 1:0] GTHE4_COMMON_RXRECCLK1SEL,
+ output wire [ 3:0] GTHE4_COMMON_SDM0FINALOUT,
+ output wire [14:0] GTHE4_COMMON_SDM0TESTDATA,
+ output wire [ 3:0] GTHE4_COMMON_SDM1FINALOUT,
+ output wire [14:0] GTHE4_COMMON_SDM1TESTDATA,
+ output wire [ 9:0] GTHE4_COMMON_TCONGPO,
+ output wire [ 0:0] GTHE4_COMMON_TCONRSVDOUT0
+
+);
+
+
+ // -------------------------------------------------------------------------------------------------------------------
+ // HDL generation of wiring and instances relating to GTHE4_COMMON primitive
+ // -------------------------------------------------------------------------------------------------------------------
+
+ generate if (1) begin : gthe4_common_gen
+
+ // for each GTHE4_COMMON primitive input port, declare a properly-sized vector
+ wire [ 0:0] GTHE4_COMMON_BGBYPASSB_int;
+ wire [ 0:0] GTHE4_COMMON_BGMONITORENB_int;
+ wire [ 0:0] GTHE4_COMMON_BGPDB_int;
+ wire [ 4:0] GTHE4_COMMON_BGRCALOVRD_int;
+ wire [ 0:0] GTHE4_COMMON_BGRCALOVRDENB_int;
+ wire [15:0] GTHE4_COMMON_DRPADDR_int;
+ wire [ 0:0] GTHE4_COMMON_DRPCLK_int;
+ wire [15:0] GTHE4_COMMON_DRPDI_int;
+ wire [ 0:0] GTHE4_COMMON_DRPEN_int;
+ wire [ 0:0] GTHE4_COMMON_DRPWE_int;
+ wire [ 0:0] GTHE4_COMMON_GTGREFCLK0_int;
+ wire [ 0:0] GTHE4_COMMON_GTGREFCLK1_int;
+ wire [ 0:0] GTHE4_COMMON_GTNORTHREFCLK00_int;
+ wire [ 0:0] GTHE4_COMMON_GTNORTHREFCLK01_int;
+ wire [ 0:0] GTHE4_COMMON_GTNORTHREFCLK10_int;
+ wire [ 0:0] GTHE4_COMMON_GTNORTHREFCLK11_int;
+ wire [ 0:0] GTHE4_COMMON_GTREFCLK00_int;
+ wire [ 0:0] GTHE4_COMMON_GTREFCLK01_int;
+ wire [ 0:0] GTHE4_COMMON_GTREFCLK10_int;
+ wire [ 0:0] GTHE4_COMMON_GTREFCLK11_int;
+ wire [ 0:0] GTHE4_COMMON_GTSOUTHREFCLK00_int;
+ wire [ 0:0] GTHE4_COMMON_GTSOUTHREFCLK01_int;
+ wire [ 0:0] GTHE4_COMMON_GTSOUTHREFCLK10_int;
+ wire [ 0:0] GTHE4_COMMON_GTSOUTHREFCLK11_int;
+ wire [ 2:0] GTHE4_COMMON_PCIERATEQPLL0_int;
+ wire [ 2:0] GTHE4_COMMON_PCIERATEQPLL1_int;
+ wire [ 7:0] GTHE4_COMMON_PMARSVD0_int;
+ wire [ 7:0] GTHE4_COMMON_PMARSVD1_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL0CLKRSVD0_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL0CLKRSVD1_int;
+ wire [ 7:0] GTHE4_COMMON_QPLL0FBDIV_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL0LOCKDETCLK_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL0LOCKEN_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL0PD_int;
+ wire [ 2:0] GTHE4_COMMON_QPLL0REFCLKSEL_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL0RESET_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL1CLKRSVD0_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL1CLKRSVD1_int;
+ wire [ 7:0] GTHE4_COMMON_QPLL1FBDIV_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL1LOCKDETCLK_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL1LOCKEN_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL1PD_int;
+ wire [ 2:0] GTHE4_COMMON_QPLL1REFCLKSEL_int;
+ wire [ 0:0] GTHE4_COMMON_QPLL1RESET_int;
+ wire [ 7:0] GTHE4_COMMON_QPLLRSVD1_int;
+ wire [ 4:0] GTHE4_COMMON_QPLLRSVD2_int;
+ wire [ 4:0] GTHE4_COMMON_QPLLRSVD3_int;
+ wire [ 7:0] GTHE4_COMMON_QPLLRSVD4_int;
+ wire [ 0:0] GTHE4_COMMON_RCALENB_int;
+ wire [24:0] GTHE4_COMMON_SDM0DATA_int;
+ wire [ 0:0] GTHE4_COMMON_SDM0RESET_int;
+ wire [ 0:0] GTHE4_COMMON_SDM0TOGGLE_int;
+ wire [ 1:0] GTHE4_COMMON_SDM0WIDTH_int;
+ wire [24:0] GTHE4_COMMON_SDM1DATA_int;
+ wire [ 0:0] GTHE4_COMMON_SDM1RESET_int;
+ wire [ 0:0] GTHE4_COMMON_SDM1TOGGLE_int;
+ wire [ 1:0] GTHE4_COMMON_SDM1WIDTH_int;
+ wire [ 9:0] GTHE4_COMMON_TCONGPI_int;
+ wire [ 0:0] GTHE4_COMMON_TCONPOWERUP_int;
+ wire [ 1:0] GTHE4_COMMON_TCONRESET_int;
+ wire [ 1:0] GTHE4_COMMON_TCONRSVDIN1_int;
+
+ // assign each vector either the corresponding tie-off value or the corresponding input port
+ if (GTHE4_COMMON_BGBYPASSB_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_BGBYPASSB_int = GTHE4_COMMON_BGBYPASSB_VAL;
+ else
+ assign GTHE4_COMMON_BGBYPASSB_int = GTHE4_COMMON_BGBYPASSB;
+
+ if (GTHE4_COMMON_BGMONITORENB_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_BGMONITORENB_int = GTHE4_COMMON_BGMONITORENB_VAL;
+ else
+ assign GTHE4_COMMON_BGMONITORENB_int = GTHE4_COMMON_BGMONITORENB;
+
+ if (GTHE4_COMMON_BGPDB_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_BGPDB_int = GTHE4_COMMON_BGPDB_VAL;
+ else
+ assign GTHE4_COMMON_BGPDB_int = GTHE4_COMMON_BGPDB;
+
+ if (GTHE4_COMMON_BGRCALOVRD_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_BGRCALOVRD_int = GTHE4_COMMON_BGRCALOVRD_VAL;
+ else
+ assign GTHE4_COMMON_BGRCALOVRD_int = GTHE4_COMMON_BGRCALOVRD;
+
+ if (GTHE4_COMMON_BGRCALOVRDENB_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_BGRCALOVRDENB_int = GTHE4_COMMON_BGRCALOVRDENB_VAL;
+ else
+ assign GTHE4_COMMON_BGRCALOVRDENB_int = GTHE4_COMMON_BGRCALOVRDENB;
+
+ if (GTHE4_COMMON_DRPADDR_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_DRPADDR_int = GTHE4_COMMON_DRPADDR_VAL;
+ else
+ assign GTHE4_COMMON_DRPADDR_int = GTHE4_COMMON_DRPADDR;
+
+ if (GTHE4_COMMON_DRPCLK_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_DRPCLK_int = GTHE4_COMMON_DRPCLK_VAL;
+ else
+ assign GTHE4_COMMON_DRPCLK_int = GTHE4_COMMON_DRPCLK;
+
+ if (GTHE4_COMMON_DRPDI_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_DRPDI_int = GTHE4_COMMON_DRPDI_VAL;
+ else
+ assign GTHE4_COMMON_DRPDI_int = GTHE4_COMMON_DRPDI;
+
+ if (GTHE4_COMMON_DRPEN_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_DRPEN_int = GTHE4_COMMON_DRPEN_VAL;
+ else
+ assign GTHE4_COMMON_DRPEN_int = GTHE4_COMMON_DRPEN;
+
+ if (GTHE4_COMMON_DRPWE_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_DRPWE_int = GTHE4_COMMON_DRPWE_VAL;
+ else
+ assign GTHE4_COMMON_DRPWE_int = GTHE4_COMMON_DRPWE;
+
+ if (GTHE4_COMMON_GTGREFCLK0_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTGREFCLK0_int = GTHE4_COMMON_GTGREFCLK0_VAL;
+ else
+ assign GTHE4_COMMON_GTGREFCLK0_int = GTHE4_COMMON_GTGREFCLK0;
+
+ if (GTHE4_COMMON_GTGREFCLK1_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTGREFCLK1_int = GTHE4_COMMON_GTGREFCLK1_VAL;
+ else
+ assign GTHE4_COMMON_GTGREFCLK1_int = GTHE4_COMMON_GTGREFCLK1;
+
+ if (GTHE4_COMMON_GTNORTHREFCLK00_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTNORTHREFCLK00_int = GTHE4_COMMON_GTNORTHREFCLK00_VAL;
+ else
+ assign GTHE4_COMMON_GTNORTHREFCLK00_int = GTHE4_COMMON_GTNORTHREFCLK00;
+
+ if (GTHE4_COMMON_GTNORTHREFCLK01_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTNORTHREFCLK01_int = GTHE4_COMMON_GTNORTHREFCLK01_VAL;
+ else
+ assign GTHE4_COMMON_GTNORTHREFCLK01_int = GTHE4_COMMON_GTNORTHREFCLK01;
+
+ if (GTHE4_COMMON_GTNORTHREFCLK10_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTNORTHREFCLK10_int = GTHE4_COMMON_GTNORTHREFCLK10_VAL;
+ else
+ assign GTHE4_COMMON_GTNORTHREFCLK10_int = GTHE4_COMMON_GTNORTHREFCLK10;
+
+ if (GTHE4_COMMON_GTNORTHREFCLK11_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTNORTHREFCLK11_int = GTHE4_COMMON_GTNORTHREFCLK11_VAL;
+ else
+ assign GTHE4_COMMON_GTNORTHREFCLK11_int = GTHE4_COMMON_GTNORTHREFCLK11;
+
+ if (GTHE4_COMMON_GTREFCLK00_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTREFCLK00_int = GTHE4_COMMON_GTREFCLK00_VAL;
+ else
+ assign GTHE4_COMMON_GTREFCLK00_int = GTHE4_COMMON_GTREFCLK00;
+
+ if (GTHE4_COMMON_GTREFCLK01_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTREFCLK01_int = GTHE4_COMMON_GTREFCLK01_VAL;
+ else
+ assign GTHE4_COMMON_GTREFCLK01_int = GTHE4_COMMON_GTREFCLK01;
+
+ if (GTHE4_COMMON_GTREFCLK10_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTREFCLK10_int = GTHE4_COMMON_GTREFCLK10_VAL;
+ else
+ assign GTHE4_COMMON_GTREFCLK10_int = GTHE4_COMMON_GTREFCLK10;
+
+ if (GTHE4_COMMON_GTREFCLK11_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTREFCLK11_int = GTHE4_COMMON_GTREFCLK11_VAL;
+ else
+ assign GTHE4_COMMON_GTREFCLK11_int = GTHE4_COMMON_GTREFCLK11;
+
+ if (GTHE4_COMMON_GTSOUTHREFCLK00_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTSOUTHREFCLK00_int = GTHE4_COMMON_GTSOUTHREFCLK00_VAL;
+ else
+ assign GTHE4_COMMON_GTSOUTHREFCLK00_int = GTHE4_COMMON_GTSOUTHREFCLK00;
+
+ if (GTHE4_COMMON_GTSOUTHREFCLK01_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTSOUTHREFCLK01_int = GTHE4_COMMON_GTSOUTHREFCLK01_VAL;
+ else
+ assign GTHE4_COMMON_GTSOUTHREFCLK01_int = GTHE4_COMMON_GTSOUTHREFCLK01;
+
+ if (GTHE4_COMMON_GTSOUTHREFCLK10_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTSOUTHREFCLK10_int = GTHE4_COMMON_GTSOUTHREFCLK10_VAL;
+ else
+ assign GTHE4_COMMON_GTSOUTHREFCLK10_int = GTHE4_COMMON_GTSOUTHREFCLK10;
+
+ if (GTHE4_COMMON_GTSOUTHREFCLK11_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_GTSOUTHREFCLK11_int = GTHE4_COMMON_GTSOUTHREFCLK11_VAL;
+ else
+ assign GTHE4_COMMON_GTSOUTHREFCLK11_int = GTHE4_COMMON_GTSOUTHREFCLK11;
+
+ if (GTHE4_COMMON_PCIERATEQPLL0_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_PCIERATEQPLL0_int = GTHE4_COMMON_PCIERATEQPLL0_VAL;
+ else
+ assign GTHE4_COMMON_PCIERATEQPLL0_int = GTHE4_COMMON_PCIERATEQPLL0;
+
+ if (GTHE4_COMMON_PCIERATEQPLL1_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_PCIERATEQPLL1_int = GTHE4_COMMON_PCIERATEQPLL1_VAL;
+ else
+ assign GTHE4_COMMON_PCIERATEQPLL1_int = GTHE4_COMMON_PCIERATEQPLL1;
+
+ if (GTHE4_COMMON_PMARSVD0_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_PMARSVD0_int = GTHE4_COMMON_PMARSVD0_VAL;
+ else
+ assign GTHE4_COMMON_PMARSVD0_int = GTHE4_COMMON_PMARSVD0;
+
+ if (GTHE4_COMMON_PMARSVD1_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_PMARSVD1_int = GTHE4_COMMON_PMARSVD1_VAL;
+ else
+ assign GTHE4_COMMON_PMARSVD1_int = GTHE4_COMMON_PMARSVD1;
+
+ if (GTHE4_COMMON_QPLL0CLKRSVD0_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL0CLKRSVD0_int = GTHE4_COMMON_QPLL0CLKRSVD0_VAL;
+ else
+ assign GTHE4_COMMON_QPLL0CLKRSVD0_int = GTHE4_COMMON_QPLL0CLKRSVD0;
+
+ if (GTHE4_COMMON_QPLL0CLKRSVD1_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL0CLKRSVD1_int = GTHE4_COMMON_QPLL0CLKRSVD1_VAL;
+ else
+ assign GTHE4_COMMON_QPLL0CLKRSVD1_int = GTHE4_COMMON_QPLL0CLKRSVD1;
+
+ if (GTHE4_COMMON_QPLL0FBDIV_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL0FBDIV_int = GTHE4_COMMON_QPLL0FBDIV_VAL;
+ else
+ assign GTHE4_COMMON_QPLL0FBDIV_int = GTHE4_COMMON_QPLL0FBDIV;
+
+ if (GTHE4_COMMON_QPLL0LOCKDETCLK_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL0LOCKDETCLK_int = GTHE4_COMMON_QPLL0LOCKDETCLK_VAL;
+ else
+ assign GTHE4_COMMON_QPLL0LOCKDETCLK_int = GTHE4_COMMON_QPLL0LOCKDETCLK;
+
+ if (GTHE4_COMMON_QPLL0LOCKEN_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL0LOCKEN_int = GTHE4_COMMON_QPLL0LOCKEN_VAL;
+ else
+ assign GTHE4_COMMON_QPLL0LOCKEN_int = GTHE4_COMMON_QPLL0LOCKEN;
+
+ if (GTHE4_COMMON_QPLL0PD_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL0PD_int = GTHE4_COMMON_QPLL0PD_VAL;
+ else
+ assign GTHE4_COMMON_QPLL0PD_int = GTHE4_COMMON_QPLL0PD;
+
+ if (GTHE4_COMMON_QPLL0REFCLKSEL_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL0REFCLKSEL_int = GTHE4_COMMON_QPLL0REFCLKSEL_VAL;
+ else
+ assign GTHE4_COMMON_QPLL0REFCLKSEL_int = GTHE4_COMMON_QPLL0REFCLKSEL;
+
+ if (GTHE4_COMMON_QPLL0RESET_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL0RESET_int = GTHE4_COMMON_QPLL0RESET_VAL;
+ else
+ assign GTHE4_COMMON_QPLL0RESET_int = GTHE4_COMMON_QPLL0RESET;
+
+ if (GTHE4_COMMON_QPLL1CLKRSVD0_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL1CLKRSVD0_int = GTHE4_COMMON_QPLL1CLKRSVD0_VAL;
+ else
+ assign GTHE4_COMMON_QPLL1CLKRSVD0_int = GTHE4_COMMON_QPLL1CLKRSVD0;
+
+ if (GTHE4_COMMON_QPLL1CLKRSVD1_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL1CLKRSVD1_int = GTHE4_COMMON_QPLL1CLKRSVD1_VAL;
+ else
+ assign GTHE4_COMMON_QPLL1CLKRSVD1_int = GTHE4_COMMON_QPLL1CLKRSVD1;
+
+ if (GTHE4_COMMON_QPLL1FBDIV_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL1FBDIV_int = GTHE4_COMMON_QPLL1FBDIV_VAL;
+ else
+ assign GTHE4_COMMON_QPLL1FBDIV_int = GTHE4_COMMON_QPLL1FBDIV;
+
+ if (GTHE4_COMMON_QPLL1LOCKDETCLK_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL1LOCKDETCLK_int = GTHE4_COMMON_QPLL1LOCKDETCLK_VAL;
+ else
+ assign GTHE4_COMMON_QPLL1LOCKDETCLK_int = GTHE4_COMMON_QPLL1LOCKDETCLK;
+
+ if (GTHE4_COMMON_QPLL1LOCKEN_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL1LOCKEN_int = GTHE4_COMMON_QPLL1LOCKEN_VAL;
+ else
+ assign GTHE4_COMMON_QPLL1LOCKEN_int = GTHE4_COMMON_QPLL1LOCKEN;
+
+ if (GTHE4_COMMON_QPLL1PD_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL1PD_int = GTHE4_COMMON_QPLL1PD_VAL;
+ else
+ assign GTHE4_COMMON_QPLL1PD_int = GTHE4_COMMON_QPLL1PD;
+
+ if (GTHE4_COMMON_QPLL1REFCLKSEL_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL1REFCLKSEL_int = GTHE4_COMMON_QPLL1REFCLKSEL_VAL;
+ else
+ assign GTHE4_COMMON_QPLL1REFCLKSEL_int = GTHE4_COMMON_QPLL1REFCLKSEL;
+
+ if (GTHE4_COMMON_QPLL1RESET_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLL1RESET_int = GTHE4_COMMON_QPLL1RESET_VAL;
+ else
+ assign GTHE4_COMMON_QPLL1RESET_int = GTHE4_COMMON_QPLL1RESET;
+
+ if (GTHE4_COMMON_QPLLRSVD1_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLLRSVD1_int = GTHE4_COMMON_QPLLRSVD1_VAL;
+ else
+ assign GTHE4_COMMON_QPLLRSVD1_int = GTHE4_COMMON_QPLLRSVD1;
+
+ if (GTHE4_COMMON_QPLLRSVD2_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLLRSVD2_int = GTHE4_COMMON_QPLLRSVD2_VAL;
+ else
+ assign GTHE4_COMMON_QPLLRSVD2_int = GTHE4_COMMON_QPLLRSVD2;
+
+ if (GTHE4_COMMON_QPLLRSVD3_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLLRSVD3_int = GTHE4_COMMON_QPLLRSVD3_VAL;
+ else
+ assign GTHE4_COMMON_QPLLRSVD3_int = GTHE4_COMMON_QPLLRSVD3;
+
+ if (GTHE4_COMMON_QPLLRSVD4_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_QPLLRSVD4_int = GTHE4_COMMON_QPLLRSVD4_VAL;
+ else
+ assign GTHE4_COMMON_QPLLRSVD4_int = GTHE4_COMMON_QPLLRSVD4;
+
+ if (GTHE4_COMMON_RCALENB_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_RCALENB_int = GTHE4_COMMON_RCALENB_VAL;
+ else
+ assign GTHE4_COMMON_RCALENB_int = GTHE4_COMMON_RCALENB;
+
+ if (GTHE4_COMMON_SDM0DATA_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_SDM0DATA_int = GTHE4_COMMON_SDM0DATA_VAL;
+ else
+ assign GTHE4_COMMON_SDM0DATA_int = GTHE4_COMMON_SDM0DATA;
+
+ if (GTHE4_COMMON_SDM0RESET_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_SDM0RESET_int = GTHE4_COMMON_SDM0RESET_VAL;
+ else
+ assign GTHE4_COMMON_SDM0RESET_int = GTHE4_COMMON_SDM0RESET;
+
+ if (GTHE4_COMMON_SDM0TOGGLE_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_SDM0TOGGLE_int = GTHE4_COMMON_SDM0TOGGLE_VAL;
+ else
+ assign GTHE4_COMMON_SDM0TOGGLE_int = GTHE4_COMMON_SDM0TOGGLE;
+
+ if (GTHE4_COMMON_SDM0WIDTH_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_SDM0WIDTH_int = GTHE4_COMMON_SDM0WIDTH_VAL;
+ else
+ assign GTHE4_COMMON_SDM0WIDTH_int = GTHE4_COMMON_SDM0WIDTH;
+
+ if (GTHE4_COMMON_SDM1DATA_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_SDM1DATA_int = GTHE4_COMMON_SDM1DATA_VAL;
+ else
+ assign GTHE4_COMMON_SDM1DATA_int = GTHE4_COMMON_SDM1DATA;
+
+ if (GTHE4_COMMON_SDM1RESET_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_SDM1RESET_int = GTHE4_COMMON_SDM1RESET_VAL;
+ else
+ assign GTHE4_COMMON_SDM1RESET_int = GTHE4_COMMON_SDM1RESET;
+
+ if (GTHE4_COMMON_SDM1TOGGLE_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_SDM1TOGGLE_int = GTHE4_COMMON_SDM1TOGGLE_VAL;
+ else
+ assign GTHE4_COMMON_SDM1TOGGLE_int = GTHE4_COMMON_SDM1TOGGLE;
+
+ if (GTHE4_COMMON_SDM1WIDTH_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_SDM1WIDTH_int = GTHE4_COMMON_SDM1WIDTH_VAL;
+ else
+ assign GTHE4_COMMON_SDM1WIDTH_int = GTHE4_COMMON_SDM1WIDTH;
+
+ if (GTHE4_COMMON_TCONGPI_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_TCONGPI_int = GTHE4_COMMON_TCONGPI_VAL;
+ else
+ assign GTHE4_COMMON_TCONGPI_int = GTHE4_COMMON_TCONGPI;
+
+ if (GTHE4_COMMON_TCONPOWERUP_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_TCONPOWERUP_int = GTHE4_COMMON_TCONPOWERUP_VAL;
+ else
+ assign GTHE4_COMMON_TCONPOWERUP_int = GTHE4_COMMON_TCONPOWERUP;
+
+ if (GTHE4_COMMON_TCONRESET_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_TCONRESET_int = GTHE4_COMMON_TCONRESET_VAL;
+ else
+ assign GTHE4_COMMON_TCONRESET_int = GTHE4_COMMON_TCONRESET;
+
+ if (GTHE4_COMMON_TCONRSVDIN1_TIE_EN == 1'b1)
+ assign GTHE4_COMMON_TCONRSVDIN1_int = GTHE4_COMMON_TCONRSVDIN1_VAL;
+ else
+ assign GTHE4_COMMON_TCONRSVDIN1_int = GTHE4_COMMON_TCONRSVDIN1;
+
+ // generate the GTHE4_COMMON primitive instance, mapping parameters and ports
+ GTHE4_COMMON #(
+ .AEN_QPLL0_FBDIV (GTHE4_COMMON_AEN_QPLL0_FBDIV ),
+ .AEN_QPLL1_FBDIV (GTHE4_COMMON_AEN_QPLL1_FBDIV ),
+ .AEN_SDM0TOGGLE (GTHE4_COMMON_AEN_SDM0TOGGLE ),
+ .AEN_SDM1TOGGLE (GTHE4_COMMON_AEN_SDM1TOGGLE ),
+ .A_SDM0TOGGLE (GTHE4_COMMON_A_SDM0TOGGLE ),
+ .A_SDM1DATA_HIGH (GTHE4_COMMON_A_SDM1DATA_HIGH ),
+ .A_SDM1DATA_LOW (GTHE4_COMMON_A_SDM1DATA_LOW ),
+ .A_SDM1TOGGLE (GTHE4_COMMON_A_SDM1TOGGLE ),
+ .BIAS_CFG0 (GTHE4_COMMON_BIAS_CFG0 ),
+ .BIAS_CFG1 (GTHE4_COMMON_BIAS_CFG1 ),
+ .BIAS_CFG2 (GTHE4_COMMON_BIAS_CFG2 ),
+ .BIAS_CFG3 (GTHE4_COMMON_BIAS_CFG3 ),
+ .BIAS_CFG4 (GTHE4_COMMON_BIAS_CFG4 ),
+ .BIAS_CFG_RSVD (GTHE4_COMMON_BIAS_CFG_RSVD ),
+ .COMMON_CFG0 (GTHE4_COMMON_COMMON_CFG0 ),
+ .COMMON_CFG1 (GTHE4_COMMON_COMMON_CFG1 ),
+ .POR_CFG (GTHE4_COMMON_POR_CFG ),
+ .PPF0_CFG (GTHE4_COMMON_PPF0_CFG ),
+ .PPF1_CFG (GTHE4_COMMON_PPF1_CFG ),
+ .QPLL0CLKOUT_RATE (GTHE4_COMMON_QPLL0CLKOUT_RATE ),
+ .QPLL0_CFG0 (GTHE4_COMMON_QPLL0_CFG0 ),
+ .QPLL0_CFG1 (GTHE4_COMMON_QPLL0_CFG1 ),
+ .QPLL0_CFG1_G3 (GTHE4_COMMON_QPLL0_CFG1_G3 ),
+ .QPLL0_CFG2 (GTHE4_COMMON_QPLL0_CFG2 ),
+ .QPLL0_CFG2_G3 (GTHE4_COMMON_QPLL0_CFG2_G3 ),
+ .QPLL0_CFG3 (GTHE4_COMMON_QPLL0_CFG3 ),
+ .QPLL0_CFG4 (GTHE4_COMMON_QPLL0_CFG4 ),
+ .QPLL0_CP (GTHE4_COMMON_QPLL0_CP ),
+ .QPLL0_CP_G3 (GTHE4_COMMON_QPLL0_CP_G3 ),
+ .QPLL0_FBDIV (GTHE4_COMMON_QPLL0_FBDIV ),
+ .QPLL0_FBDIV_G3 (GTHE4_COMMON_QPLL0_FBDIV_G3 ),
+ .QPLL0_INIT_CFG0 (GTHE4_COMMON_QPLL0_INIT_CFG0 ),
+ .QPLL0_INIT_CFG1 (GTHE4_COMMON_QPLL0_INIT_CFG1 ),
+ .QPLL0_LOCK_CFG (GTHE4_COMMON_QPLL0_LOCK_CFG ),
+ .QPLL0_LOCK_CFG_G3 (GTHE4_COMMON_QPLL0_LOCK_CFG_G3 ),
+ .QPLL0_LPF (GTHE4_COMMON_QPLL0_LPF ),
+ .QPLL0_LPF_G3 (GTHE4_COMMON_QPLL0_LPF_G3 ),
+ .QPLL0_PCI_EN (GTHE4_COMMON_QPLL0_PCI_EN ),
+ .QPLL0_RATE_SW_USE_DRP (GTHE4_COMMON_QPLL0_RATE_SW_USE_DRP),
+ .QPLL0_REFCLK_DIV (GTHE4_COMMON_QPLL0_REFCLK_DIV ),
+ .QPLL0_SDM_CFG0 (GTHE4_COMMON_QPLL0_SDM_CFG0 ),
+ .QPLL0_SDM_CFG1 (GTHE4_COMMON_QPLL0_SDM_CFG1 ),
+ .QPLL0_SDM_CFG2 (GTHE4_COMMON_QPLL0_SDM_CFG2 ),
+ .QPLL1CLKOUT_RATE (GTHE4_COMMON_QPLL1CLKOUT_RATE ),
+ .QPLL1_CFG0 (GTHE4_COMMON_QPLL1_CFG0 ),
+ .QPLL1_CFG1 (GTHE4_COMMON_QPLL1_CFG1 ),
+ .QPLL1_CFG1_G3 (GTHE4_COMMON_QPLL1_CFG1_G3 ),
+ .QPLL1_CFG2 (GTHE4_COMMON_QPLL1_CFG2 ),
+ .QPLL1_CFG2_G3 (GTHE4_COMMON_QPLL1_CFG2_G3 ),
+ .QPLL1_CFG3 (GTHE4_COMMON_QPLL1_CFG3 ),
+ .QPLL1_CFG4 (GTHE4_COMMON_QPLL1_CFG4 ),
+ .QPLL1_CP (GTHE4_COMMON_QPLL1_CP ),
+ .QPLL1_CP_G3 (GTHE4_COMMON_QPLL1_CP_G3 ),
+ .QPLL1_FBDIV (GTHE4_COMMON_QPLL1_FBDIV ),
+ .QPLL1_FBDIV_G3 (GTHE4_COMMON_QPLL1_FBDIV_G3 ),
+ .QPLL1_INIT_CFG0 (GTHE4_COMMON_QPLL1_INIT_CFG0 ),
+ .QPLL1_INIT_CFG1 (GTHE4_COMMON_QPLL1_INIT_CFG1 ),
+ .QPLL1_LOCK_CFG (GTHE4_COMMON_QPLL1_LOCK_CFG ),
+ .QPLL1_LOCK_CFG_G3 (GTHE4_COMMON_QPLL1_LOCK_CFG_G3 ),
+ .QPLL1_LPF (GTHE4_COMMON_QPLL1_LPF ),
+ .QPLL1_LPF_G3 (GTHE4_COMMON_QPLL1_LPF_G3 ),
+ .QPLL1_PCI_EN (GTHE4_COMMON_QPLL1_PCI_EN ),
+ .QPLL1_RATE_SW_USE_DRP (GTHE4_COMMON_QPLL1_RATE_SW_USE_DRP),
+ .QPLL1_REFCLK_DIV (GTHE4_COMMON_QPLL1_REFCLK_DIV ),
+ .QPLL1_SDM_CFG0 (GTHE4_COMMON_QPLL1_SDM_CFG0 ),
+ .QPLL1_SDM_CFG1 (GTHE4_COMMON_QPLL1_SDM_CFG1 ),
+ .QPLL1_SDM_CFG2 (GTHE4_COMMON_QPLL1_SDM_CFG2 ),
+ .RSVD_ATTR0 (GTHE4_COMMON_RSVD_ATTR0 ),
+ .RSVD_ATTR1 (GTHE4_COMMON_RSVD_ATTR1 ),
+ .RSVD_ATTR2 (GTHE4_COMMON_RSVD_ATTR2 ),
+ .RSVD_ATTR3 (GTHE4_COMMON_RSVD_ATTR3 ),
+ .RXRECCLKOUT0_SEL (GTHE4_COMMON_RXRECCLKOUT0_SEL ),
+ .RXRECCLKOUT1_SEL (GTHE4_COMMON_RXRECCLKOUT1_SEL ),
+ .SARC_ENB (GTHE4_COMMON_SARC_ENB ),
+ .SARC_SEL (GTHE4_COMMON_SARC_SEL ),
+ .SDM0INITSEED0_0 (GTHE4_COMMON_SDM0INITSEED0_0 ),
+ .SDM0INITSEED0_1 (GTHE4_COMMON_SDM0INITSEED0_1 ),
+ .SDM1INITSEED0_0 (GTHE4_COMMON_SDM1INITSEED0_0 ),
+ .SDM1INITSEED0_1 (GTHE4_COMMON_SDM1INITSEED0_1 ),
+ .SIM_MODE (GTHE4_COMMON_SIM_MODE ),
+ .SIM_RESET_SPEEDUP (GTHE4_COMMON_SIM_RESET_SPEEDUP ),
+ .SIM_DEVICE (GTHE4_COMMON_SIM_DEVICE )
+ ) GTHE4_COMMON_PRIM_INST (
+ .BGBYPASSB (GTHE4_COMMON_BGBYPASSB_int [ 0:0]),
+ .BGMONITORENB (GTHE4_COMMON_BGMONITORENB_int [ 0:0]),
+ .BGPDB (GTHE4_COMMON_BGPDB_int [ 0:0]),
+ .BGRCALOVRD (GTHE4_COMMON_BGRCALOVRD_int [ 4:0]),
+ .BGRCALOVRDENB (GTHE4_COMMON_BGRCALOVRDENB_int [ 0:0]),
+ .DRPADDR (GTHE4_COMMON_DRPADDR_int [15:0]),
+ .DRPCLK (GTHE4_COMMON_DRPCLK_int [ 0:0]),
+ .DRPDI (GTHE4_COMMON_DRPDI_int [15:0]),
+ .DRPEN (GTHE4_COMMON_DRPEN_int [ 0:0]),
+ .DRPWE (GTHE4_COMMON_DRPWE_int [ 0:0]),
+ .GTGREFCLK0 (GTHE4_COMMON_GTGREFCLK0_int [ 0:0]),
+ .GTGREFCLK1 (GTHE4_COMMON_GTGREFCLK1_int [ 0:0]),
+ .GTNORTHREFCLK00 (GTHE4_COMMON_GTNORTHREFCLK00_int [ 0:0]),
+ .GTNORTHREFCLK01 (GTHE4_COMMON_GTNORTHREFCLK01_int [ 0:0]),
+ .GTNORTHREFCLK10 (GTHE4_COMMON_GTNORTHREFCLK10_int [ 0:0]),
+ .GTNORTHREFCLK11 (GTHE4_COMMON_GTNORTHREFCLK11_int [ 0:0]),
+ .GTREFCLK00 (GTHE4_COMMON_GTREFCLK00_int [ 0:0]),
+ .GTREFCLK01 (GTHE4_COMMON_GTREFCLK01_int [ 0:0]),
+ .GTREFCLK10 (GTHE4_COMMON_GTREFCLK10_int [ 0:0]),
+ .GTREFCLK11 (GTHE4_COMMON_GTREFCLK11_int [ 0:0]),
+ .GTSOUTHREFCLK00 (GTHE4_COMMON_GTSOUTHREFCLK00_int [ 0:0]),
+ .GTSOUTHREFCLK01 (GTHE4_COMMON_GTSOUTHREFCLK01_int [ 0:0]),
+ .GTSOUTHREFCLK10 (GTHE4_COMMON_GTSOUTHREFCLK10_int [ 0:0]),
+ .GTSOUTHREFCLK11 (GTHE4_COMMON_GTSOUTHREFCLK11_int [ 0:0]),
+ .PCIERATEQPLL0 (GTHE4_COMMON_PCIERATEQPLL0_int [ 2:0]),
+ .PCIERATEQPLL1 (GTHE4_COMMON_PCIERATEQPLL1_int [ 2:0]),
+ .PMARSVD0 (GTHE4_COMMON_PMARSVD0_int [ 7:0]),
+ .PMARSVD1 (GTHE4_COMMON_PMARSVD1_int [ 7:0]),
+ .QPLL0CLKRSVD0 (GTHE4_COMMON_QPLL0CLKRSVD0_int [ 0:0]),
+ .QPLL0CLKRSVD1 (GTHE4_COMMON_QPLL0CLKRSVD1_int [ 0:0]),
+ .QPLL0FBDIV (GTHE4_COMMON_QPLL0FBDIV_int [ 7:0]),
+ .QPLL0LOCKDETCLK (GTHE4_COMMON_QPLL0LOCKDETCLK_int [ 0:0]),
+ .QPLL0LOCKEN (GTHE4_COMMON_QPLL0LOCKEN_int [ 0:0]),
+ .QPLL0PD (GTHE4_COMMON_QPLL0PD_int [ 0:0]),
+ .QPLL0REFCLKSEL (GTHE4_COMMON_QPLL0REFCLKSEL_int [ 2:0]),
+ .QPLL0RESET (GTHE4_COMMON_QPLL0RESET_int [ 0:0]),
+ .QPLL1CLKRSVD0 (GTHE4_COMMON_QPLL1CLKRSVD0_int [ 0:0]),
+ .QPLL1CLKRSVD1 (GTHE4_COMMON_QPLL1CLKRSVD1_int [ 0:0]),
+ .QPLL1FBDIV (GTHE4_COMMON_QPLL1FBDIV_int [ 7:0]),
+ .QPLL1LOCKDETCLK (GTHE4_COMMON_QPLL1LOCKDETCLK_int [ 0:0]),
+ .QPLL1LOCKEN (GTHE4_COMMON_QPLL1LOCKEN_int [ 0:0]),
+ .QPLL1PD (GTHE4_COMMON_QPLL1PD_int [ 0:0]),
+ .QPLL1REFCLKSEL (GTHE4_COMMON_QPLL1REFCLKSEL_int [ 2:0]),
+ .QPLL1RESET (GTHE4_COMMON_QPLL1RESET_int [ 0:0]),
+ .QPLLRSVD1 (GTHE4_COMMON_QPLLRSVD1_int [ 7:0]),
+ .QPLLRSVD2 (GTHE4_COMMON_QPLLRSVD2_int [ 4:0]),
+ .QPLLRSVD3 (GTHE4_COMMON_QPLLRSVD3_int [ 4:0]),
+ .QPLLRSVD4 (GTHE4_COMMON_QPLLRSVD4_int [ 7:0]),
+ .RCALENB (GTHE4_COMMON_RCALENB_int [ 0:0]),
+ .SDM0DATA (GTHE4_COMMON_SDM0DATA_int [24:0]),
+ .SDM0RESET (GTHE4_COMMON_SDM0RESET_int [ 0:0]),
+ .SDM0TOGGLE (GTHE4_COMMON_SDM0TOGGLE_int [ 0:0]),
+ .SDM0WIDTH (GTHE4_COMMON_SDM0WIDTH_int [ 1:0]),
+ .SDM1DATA (GTHE4_COMMON_SDM1DATA_int [24:0]),
+ .SDM1RESET (GTHE4_COMMON_SDM1RESET_int [ 0:0]),
+ .SDM1TOGGLE (GTHE4_COMMON_SDM1TOGGLE_int [ 0:0]),
+ .SDM1WIDTH (GTHE4_COMMON_SDM1WIDTH_int [ 1:0]),
+ .TCONGPI (GTHE4_COMMON_TCONGPI_int [ 9:0]),
+ .TCONPOWERUP (GTHE4_COMMON_TCONPOWERUP_int [ 0:0]),
+ .TCONRESET (GTHE4_COMMON_TCONRESET_int [ 1:0]),
+ .TCONRSVDIN1 (GTHE4_COMMON_TCONRSVDIN1_int [ 1:0]),
+
+ .DRPDO (GTHE4_COMMON_DRPDO [15:0]),
+ .DRPRDY (GTHE4_COMMON_DRPRDY [ 0:0]),
+ .PMARSVDOUT0 (GTHE4_COMMON_PMARSVDOUT0 [ 7:0]),
+ .PMARSVDOUT1 (GTHE4_COMMON_PMARSVDOUT1 [ 7:0]),
+ .QPLL0FBCLKLOST (GTHE4_COMMON_QPLL0FBCLKLOST [ 0:0]),
+ .QPLL0LOCK (GTHE4_COMMON_QPLL0LOCK [ 0:0]),
+ .QPLL0OUTCLK (GTHE4_COMMON_QPLL0OUTCLK [ 0:0]),
+ .QPLL0OUTREFCLK (GTHE4_COMMON_QPLL0OUTREFCLK [ 0:0]),
+ .QPLL0REFCLKLOST (GTHE4_COMMON_QPLL0REFCLKLOST [ 0:0]),
+ .QPLL1FBCLKLOST (GTHE4_COMMON_QPLL1FBCLKLOST [ 0:0]),
+ .QPLL1LOCK (GTHE4_COMMON_QPLL1LOCK [ 0:0]),
+ .QPLL1OUTCLK (GTHE4_COMMON_QPLL1OUTCLK [ 0:0]),
+ .QPLL1OUTREFCLK (GTHE4_COMMON_QPLL1OUTREFCLK [ 0:0]),
+ .QPLL1REFCLKLOST (GTHE4_COMMON_QPLL1REFCLKLOST [ 0:0]),
+ .QPLLDMONITOR0 (GTHE4_COMMON_QPLLDMONITOR0 [ 7:0]),
+ .QPLLDMONITOR1 (GTHE4_COMMON_QPLLDMONITOR1 [ 7:0]),
+ .REFCLKOUTMONITOR0 (GTHE4_COMMON_REFCLKOUTMONITOR0 [ 0:0]),
+ .REFCLKOUTMONITOR1 (GTHE4_COMMON_REFCLKOUTMONITOR1 [ 0:0]),
+ .RXRECCLK0SEL (GTHE4_COMMON_RXRECCLK0SEL [ 1:0]),
+ .RXRECCLK1SEL (GTHE4_COMMON_RXRECCLK1SEL [ 1:0]),
+ .SDM0FINALOUT (GTHE4_COMMON_SDM0FINALOUT [ 3:0]),
+ .SDM0TESTDATA (GTHE4_COMMON_SDM0TESTDATA [14:0]),
+ .SDM1FINALOUT (GTHE4_COMMON_SDM1FINALOUT [ 3:0]),
+ .SDM1TESTDATA (GTHE4_COMMON_SDM1TESTDATA [14:0]),
+ .TCONGPO (GTHE4_COMMON_TCONGPO [ 9:0]),
+ .TCONRSVDOUT0 (GTHE4_COMMON_TCONRSVDOUT0 [ 0:0])
+
+ );
+
+ end
+ endgenerate
+
+
+endmodule
diff --git a/hdl/top_combpm_electron.vhd b/hdl/top_combpm_electron.vhd
index a8b0abfebe66556cee4ce5c6e18eac28a3fa4539..415a22a080060a9279136b076e3ae924093785ce 100644
--- a/hdl/top_combpm_electron.vhd
+++ b/hdl/top_combpm_electron.vhd
@@ -8,14 +8,16 @@ use ieee.numeric_std.all;
entity top_combpm_electron is
port(
- gt_clk : out std_logic; -- Data clock from GT
- rst_n : in std_logic; -- Asyncheonous reset
+
+ rst_n : in std_logic; -- Asynchronous reset
free_100_clk : in std_logic; -- Freerunning clock for GT
+ clk : out std_logic; -- main clock (AXIS and AXI-MM)
- -- Differential reference clock inputs and buffered output
- mgtref_clk_p : in std_logic;
- mgtref_clk_n : in std_logic;
- mgtref_buf_clk : out std_logic;
+ -- Transceiver QPLL interface
+ qpll_out_clk : in std_logic; -- QPLL clock for transceivers
+ qpll_ref_clk : in std_logic; -- QPLL ref clock
+ qpll_reset : out std_logic; -- QPLL reset
+ qpll_lock : in std_logic; -- QPLL is locked
-- SFP interfaces
sfp_txp : out std_logic;
@@ -73,8 +75,7 @@ architecture struct of top_combpm_electron is
ATTRIBUTE X_INTERFACE_PARAMETER of rst_n : SIGNAL is "POLARITY ACTIVE_LOW";
ATTRIBUTE X_INTERFACE_PARAMETER of free_100_clk: SIGNAL is "FREQ_HZ 100000000";
- ATTRIBUTE X_INTERFACE_PARAMETER of mgtref_buf_clk: SIGNAL is "FREQ_HZ 156250000";
- ATTRIBUTE X_INTERFACE_PARAMETER of gt_clk: SIGNAL is "FREQ_HZ 156250000, ASSOCIATED_BUSIF m_axis:s_axi";
+ ATTRIBUTE X_INTERFACE_PARAMETER of clk: SIGNAL is "FREQ_HZ 156250000, ASSOCIATED_BUSIF m_axis:s_axi";
ATTRIBUTE X_INTERFACE_INFO of sfp_txn: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TXN";
ATTRIBUTE X_INTERFACE_INFO of sfp_rxn: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp RXN";
@@ -85,27 +86,19 @@ architecture struct of top_combpm_electron is
ATTRIBUTE X_INTERFACE_INFO of sfp_tx_disable: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TX_DISABLE";
ATTRIBUTE X_INTERFACE_INFO of sfp_tx_fault: SIGNAL is "xilinx.com:interface:sfp:1.0 sfp TX_FAULT";
- ATTRIBUTE X_INTERFACE_INFO of mgtref_clk_p: SIGNAL is "xilinx.com:interface:diff_clock:1.0 mgtrefclk CLK_P";
- ATTRIBUTE X_INTERFACE_INFO of mgtref_clk_n: SIGNAL is "xilinx.com:interface:diff_clock:1.0 mgtrefclk CLK_N";
- ATTRIBUTE X_INTERFACE_PARAMETER of mgtref_clk_p: SIGNAL is "FREQ_HZ 156250000";
-
------------------------
-- SIGNAL DECLARATION --
------------------------
- signal sync_rst : std_logic; -- Reset synchonized to clock
signal rst : std_logic;
signal tx_disable : std_logic;
signal rx_commadeten : std_logic;
- signal srst_gt : std_logic;
signal frame_counter : std_logic_vector(15 downto 0);
signal frame_error : std_logic;
- signal gt_usrclk : std_logic;
signal gt_datarx : std_logic_vector(15 downto 0);
signal gt_datatx : std_logic_vector(15 downto 0);
signal gt_powergood : std_logic;
- signal gt_qplllock : std_logic;
signal gt_txclkactive : std_logic;
signal gt_rxclkactive : std_logic;
signal gt_txresetdone : std_logic;
@@ -120,18 +113,10 @@ architecture struct of top_combpm_electron is
signal gt_rxcommadeten : std_logic;
signal gt_txdisable : std_logic;
signal gt_rxcdrlock : std_logic;
+ signal gt_rxresetdatapath : std_logic;
begin
- ---------------------------
- -- RESET SYNCHRONIZATION --
- ---------------------------
- inst_cdc_arst: xpm_cdc_async_rst
- port map(
- src_arst => rst,
- dest_clk => gt_clk,
- dest_arst => sync_rst
- );
-- Reset invert polarity
rst <= not rst_n;
@@ -149,7 +134,7 @@ begin
sfp_modabs_i => gt_modabs,
sfp_txdisable_o => tx_disable,
gt_powergood_i => gt_powergood,
- gt_qplllock_i => gt_qplllock,
+ gt_qplllock_i => qpll_lock,
gt_txclkactive_i => gt_txclkactive,
gt_rxclkactive_i => gt_rxclkactive,
gt_rxcdrlock_i => gt_rxcdrlock,
@@ -159,11 +144,11 @@ begin
gt_rxbyterealign_i => gt_rxbyterealign,
gt_rxcommadet_i => gt_rxcommadet,
gt_rxcommadeten_o => rx_commadeten,
- gt_rstall_o => srst_gt,
+ gt_rxresetdatapath_o => gt_rxresetdatapath,
protocol_framecnt_i => frame_counter,
protocol_frameerror_i => frame_error,
- clk => gt_usrclk,
+ clk => clk,
reset => sync_rst,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWPROT => S_AXI_AWPROT,
@@ -192,11 +177,11 @@ begin
protocol_inst: entity work.combpm_protocol_electron
port map(
rst_n => rst_n,
- clk => gt_usrclk,
+ clk => clk,
gt_datarx => gt_datarx,
gt_datatx => gt_datatx,
gt_powergood => gt_powergood,
- gt_qplllock => gt_qplllock,
+ gt_qplllock => qpll_lock,
gt_txclkactive => gt_txclkactive,
gt_rxclkactive => gt_rxclkactive,
gt_txresetdone => gt_txresetdone,
@@ -224,62 +209,91 @@ begin
tx_disable_i => tx_disable,
rx_commadeten_i => rx_commadeten,
- srst_gt_i => srst_gt,
+ srst_gt_i => gt_rxresetdatapath,
frame_counter_o => frame_counter,
frame_error_o => frame_error
);
- ----------------
- -- GT WRAPPER --
- ----------------
- gt_clk <= gt_usrclk;
- inst_gtwrapper: entity work.combpm_gtwrapper
- port map(
- -- 100MHz clock, main ref clock
- clk_100 => free_100_clk,
-
- -- Usrclock for data transfer
- usrclk => gt_usrclk,
-
- -- Async reset active low
- rst_n => rst_n,
-
- -- Differential reference clock inputs and buffered output
- mgtrefclk_p => mgtref_clk_p,
- mgtrefclk_n => mgtref_clk_n,
- mgtrefclk => mgtref_buf_clk,
-
- -- SFP interfaces
- sfp_txp(0) => sfp_txp,
- sfp_txn(0) => sfp_txn,
- sfp_rxp(0) => sfp_rxp,
- sfp_rxn(0) => sfp_rxn,
- sfp_rx_los(0) => sfp_rx_los,
- sfp_mod_abs(0) => sfp_mod_abs,
- sfp_tx_disable(0) => sfp_tx_disable,
- sfp_tx_fault(0) => sfp_tx_fault,
-
- -- GT interfaces
- gt_datarx => gt_datarx,
- gt_datatx => gt_datatx,
- gt_powergood(0) => gt_powergood,
- gt_qplllock(0) => gt_qplllock,
- gt_txclkactive(0) => gt_txclkactive,
- gt_rxclkactive(0) => gt_rxclkactive,
- gt_txresetdone(0) => gt_txresetdone,
- gt_rxresetdone(0) => gt_rxresetdone,
- gt_rxbyteisaligned(0) => gt_rxbyteisaligned,
- gt_rxbyterealign(0) => gt_rxbyterealign,
- gt_rxcommadet(0) => gt_rxcommadet,
- gt_txfault(0) => gt_txfault,
- gt_rxlos(0) => gt_rxlos,
- gt_rxcdrlock(0) => gt_rxcdrlock,
- gt_modabs(0) => gt_modabs,
- gt_rstall(0) => gt_rstall,
- gt_rxcommadeten(0) => gt_rxcommadeten,
- gt_txdisable(0) => gt_txdisable
+ ---------------
+ -- GT WIZARD --
+ ---------------
+ gtwizard_inst : combpm_gtwizard
+ PORT MAP (
+ -- Async reset
+ gtwiz_reset_all_in(0) => rst,
+ gtwiz_userclk_tx_reset_in(0) => rst,
+ gtwiz_userclk_rx_reset_in(0) => rst,
+
+ -- Free run clock
+ gtwiz_reset_clk_freerun_in(0) => free_100_clk,
+
+ -- Clock and data
+ gtwiz_userclk_rx_usrclk_out(0) => clk,
+ gtwiz_userdata_tx_in => gt_datatx,
+ gtwiz_userdata_rx_out => gt_datarx,
+
+ -- QPLL COMMON
+ gtwiz_reset_qpll1lock_in(0) => qpll_lock,
+ gtwiz_reset_qpll1reset_out(0) => qpll_reset,
+ qpll1clk_in(0) => qpll_out_clk,
+ qpll1refclk_in(0) => qpll_ref_clk,
+
+ -- Control
+ gtwiz_reset_rx_datapath_in(0) => gt_rxresetdatapath,
+ rxbufreset_in(0) => "0",
+ rxcommadeten_in(0) => gt_rxcommadeten,
+ rx8b10ben_in => "1",
+ rxmcommaalignen_in => "1",
+ rxpcommaalignen_in => "1",
+ tx8b10ben_in => "1",
+ gtwiz_reset_tx_pll_and_datapath_in => "0",
+ gtwiz_reset_tx_datapath_in => "0",
+ gtwiz_reset_rx_pll_and_datapath_in => "0",
+
+ -- Status
+ gtwiz_userclk_tx_active_out(0) => gt_txclkactive,
+ gtwiz_userclk_rx_active_out(0) => gt_rxclkactive,
+ gtwiz_reset_tx_done_out(0) => gt_txresetdone,
+ gtwiz_reset_rx_done_out(0) => gt_rxresetdone,
+ gtpowergood_out(0) => gt_powergood,
+ rxbyteisaligned_out(0) => gt_rxbyteisaligned,
+ rxbyterealign_out(0) => gt_rxbyterealign,
+ rxcdrlock_out(0) => gt_rxcdrlock,
+ rxcommadet_out(0) => gt_rxcommadet,
+ rxbufstatus_out => open,
+ rxclkcorcnt_out => open,
+ rxpmaresetdone_out => open,
+ txpmaresetdone_out => open,
+
+ -- SFP
+ gthrxn_in(0) => sfp_rxn,
+ gthrxp_in(0) => sfp_rxp,
+ gthtxn_out => sfp_txn,
+ gthtxp_out => sfp_txp,
+
+ -- Not used
+ qpll0clk_in => "0", -- not used
+ qpll0refclk_in => "0", -- not used
+ gtwiz_reset_rx_cdr_stable_out => open, -- Do not use
+ gtwiz_userclk_rx_srcclk_out => open,
+ gtwiz_userclk_rx_usrclk2_out => open,
+ rxctrl0_out => (others => '0'),
+ rxctrl1_out => (others => '0'),
+ rxctrl2_out => (others => '0'),
+ rxctrl3_out => (others => '0'),
+ txctrl0_in => (others => '0'),
+ txctrl1_in => (others => '0'),
+ txctrl2_in => (others => '0'),
+ gtwiz_userclk_tx_srcclk_out => open,
+ gtwiz_userclk_tx_usrclk_out => open,
+ gtwiz_userclk_tx_usrclk2_out => open
);
+ -- SFP direct connexion
+ gt_txfault <= sfp_tx_fault;
+ gt_rxlos <= sfp_rx_los;
+ gt_modabs <= sfp_mod_abs;
+ sfp_tx_disable <= gt_txdisable;
end architecture struct;
diff --git a/rdl/combpm_protocol_electron_ctrl.rdl b/rdl/combpm_protocol_electron_ctrl.rdl
index 30fffa00a9fbf568f9a4875f45a58f61caed516f..1bfcf92f621d479325ffbf55adf6479dd6093138 100644
--- a/rdl/combpm_protocol_electron_ctrl.rdl
+++ b/rdl/combpm_protocol_electron_ctrl.rdl
@@ -103,10 +103,10 @@ addrmap combpm_protocol_electron_ctrl {
} RXCOMMADETEN = 1;
field {
- desc="Reset all";
+ desc="Reset RX datapath";
hw=r;
sw=rw;
- } RSTALL = 1;
+ } RXRSTDATAPATH = 1;
} GT;
diff --git a/tcl/generate_gtwizard.tcl b/tcl/generate_gtwizard.tcl
index 1f0b6ff4c438925437300acbe5fea25876b10419..67b6e0a330be7be6de7121c3ad3227743e2fb4e4 100644
--- a/tcl/generate_gtwizard.tcl
+++ b/tcl/generate_gtwizard.tcl
@@ -35,15 +35,24 @@ set_property -dict [list \
CONFIG.RX_CC_K_0_0 {true} \
CONFIG.RX_CC_VAL_0_1 {10010101} \
CONFIG.RX_CC_K_0_1 {true} \
- CONFIG.ENABLE_OPTIONAL_PORTS {qpll1lock_out rxcdrlock_out} \
+ CONFIG.ENABLE_OPTIONAL_PORTS {rxcdrlock_out} \
CONFIG.RX_REFCLK_SOURCE {X0Y4 clk1} \
CONFIG.TX_REFCLK_SOURCE {X0Y4 clk1} \
CONFIG.LOCATE_TX_USER_CLOCKING {CORE} \
CONFIG.LOCATE_RX_USER_CLOCKING {CORE} \
+ CONFIG.LOCATE_COMMON {EXAMPLE_DESIGN} \
+ CONFIG.LOCATE_RESET_CONTROLLER {CORE} \
+ CONFIG.LOCATE_USER_DATA_WIDTH_SIZING {CORE} \
CONFIG.TXPROGDIV_FREQ_SOURCE {QPLL1} \
CONFIG.TXPROGDIV_FREQ_VAL {106} \
CONFIG.FREERUN_FREQUENCY {100} \
] [get_ips ${module_name}]
+# If using 2 ports
+# CONFIG.CHANNEL_ENABLE {X0Y4 X0Y5}
+# CONFIG.RX_REFCLK_SOURCE {X0Y5 clk1 X0Y4 clk1}
+# CONFIG.TX_REFCLK_SOURCE {X0Y5 clk1 X0Y4 clk1}
+
+
# Generate output products
generate_target all [get_ips ${module_name}]
diff --git a/tcl/metadata.tcl b/tcl/metadata.tcl
index ab54487fdab22dc2605f3e41b320e8ba77d88bb9..d0c1c6fea1bd3dbbaeeb778faf5722da9dc93872 100644
--- a/tcl/metadata.tcl
+++ b/tcl/metadata.tcl
@@ -2,8 +2,10 @@ set design "combpm"
set top top_combpm_electron
set part "xczu11eg-ffvc1760-2L-e"
+set vlnv_vendor "synchrotron-soleil.fr"
+
set ip_properties [ list \
- vendor "synchrotron-soleil.fr" \
+ vendor ${vlnv_vendor} \
library "user" \
name ${design} \
version "1.0" \