From 535b62f6a48e52266ac47b7fbe0245991bf5f938 Mon Sep 17 00:00:00 2001
From: Romain Broucquart <romain.broucquart@synchrotron-soleil.fr>
Date: Fri, 15 Apr 2022 16:58:01 +0200
Subject: [PATCH] Fix GT Wizard creation
* Put configuration in a variable to print it
* Put the quad_name in a variable, not fully used by now.
* Set the target FPGA in the TCL.
---
tcl/combpm_gtwizard.tcl | 28 ++++++++++++++++------------
tcl/main.tcl | 5 +++++
2 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/tcl/combpm_gtwizard.tcl b/tcl/combpm_gtwizard.tcl
index d22a0c8..170b84b 100644
--- a/tcl/combpm_gtwizard.tcl
+++ b/tcl/combpm_gtwizard.tcl
@@ -1,15 +1,11 @@
# Create a GTWizard IP for one quad.
+set quad_name "X0Y4"
set module_name "combpm_gtwizard"
-set quad_name X0Y4
-# Create IP
-create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -version 1.7 -module_name ${module_name}
-
-# Configure the IP
-set_property -dict [list \
- CONFIG.CHANNEL_ENABLE {${quad_name}} \
- CONFIG.TX_MASTER_CHANNEL {${quad_name}} \
- CONFIG.RX_MASTER_CHANNEL {${quad_name}} \
+set gt_ip_config [ list \
+ CONFIG.CHANNEL_ENABLE $quad_name \
+ CONFIG.TX_MASTER_CHANNEL $quad_name \
+ CONFIG.RX_MASTER_CHANNEL $quad_name \
CONFIG.TX_LINE_RATE {2.125} \
CONFIG.TX_PLL_TYPE {QPLL1} \
CONFIG.TX_REFCLK_FREQUENCY {156.2500001} \
@@ -42,8 +38,8 @@ set_property -dict [list \
CONFIG.RX_CC_K_0_1 {false} \
CONFIG.RX_CC_PERIODICITY {100} \
CONFIG.ENABLE_OPTIONAL_PORTS {rxcdrlock_out} \
- CONFIG.RX_REFCLK_SOURCE {${quad_name} clk1} \
- CONFIG.TX_REFCLK_SOURCE {${quad_name} clk1} \
+ CONFIG.RX_REFCLK_SOURCE "$quad_name clk1" \
+ CONFIG.TX_REFCLK_SOURCE "$quad_name clk1" \
CONFIG.LOCATE_TX_USER_CLOCKING {CORE} \
CONFIG.LOCATE_RX_USER_CLOCKING {CORE} \
CONFIG.LOCATE_COMMON {EXAMPLE_DESIGN} \
@@ -54,7 +50,15 @@ set_property -dict [list \
CONFIG.FREERUN_FREQUENCY {100} \
CONFIG.SECONDARY_QPLL_ENABLE {true} \
CONFIG.SECONDARY_QPLL_REFCLK_FREQUENCY {156.25} \
- ] [get_ips ${module_name}]
+ ]
+
+puts $gt_ip_config
+
+# Create IP
+create_ip -name gtwizard_ultrascale -vendor xilinx.com -library ip -version 1.7 -module_name ${module_name}
+
+# Configure the IP
+set_property -dict $gt_ip_config [get_ips ${module_name}]
# If using 2 ports
# CONFIG.CHANNEL_ENABLE {${quad_name} X0Y5}
diff --git a/tcl/main.tcl b/tcl/main.tcl
index 9e69f07..78cfc09 100644
--- a/tcl/main.tcl
+++ b/tcl/main.tcl
@@ -27,6 +27,11 @@ proc doOnCreate {} {
variable Vhdl
addSources Vhdl
+ # TODO sould probably get that part number from the project configuration
+ set fpga_part "xczu11eg-ffvc1760-2L-e"
+ set_property part ${fpga_part} [current_project]
+ set_property target_language VHDL [current_project]
+
# Create GT wizard IP
source ../tcl/combpm_gtwizard.tcl
}
--
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