From 48e5f8d530d0035f6e5fede96d90f1cdd80694e0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Romain=20Bron=C3=A8s?= <romain.brones@synchrotron-soleil.fr>
Date: Fri, 17 Mar 2023 17:22:54 +0100
Subject: [PATCH] fix(addr):Fix table aligment
* Also change the name of the table.
* DESYRDL right shift the address by 2 before passing it to the memory.
This is equivalent of having element of 32bits.
---
hdl/top_combpm_electron.vhd | 12 ++++++------
rdl/combpm.rdl | 4 ++--
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/hdl/top_combpm_electron.vhd b/hdl/top_combpm_electron.vhd
index b8fabe4..83b9a7c 100644
--- a/hdl/top_combpm_electron.vhd
+++ b/hdl/top_combpm_electron.vhd
@@ -348,12 +348,12 @@ begin
m_axis_tvalid => m_axis_tvalid,
-- Table configuration interface
- pi_table_en => addrmap_r.table.en,
- pi_table_we => addrmap_r.table.we,
- pi_table_addr => addrmap_r.table.addr(C_W_ADDR_TABLE-1 downto 0),
- pi_table_data => addrmap_r.table.data,
- po_table_data => addrmap_w.table.data
+ pi_table_en => addrmap_r.filtertable.en,
+ pi_table_we => addrmap_r.filtertable.we,
+ pi_table_addr => addrmap_r.filtertable.addr(C_W_ADDR_TABLE-1 downto 0),
+ pi_table_data => addrmap_r.filtertable.data(7 downto 0),
+ po_table_data => addrmap_w.filtertable.data(7 downto 0)
);
-
+ addrmap_w.filtertable.data(31 downto 8) <= (others => '0');
end architecture struct;
diff --git a/rdl/combpm.rdl b/rdl/combpm.rdl
index dfd1052..4cd1004 100644
--- a/rdl/combpm.rdl
+++ b/rdl/combpm.rdl
@@ -116,8 +116,8 @@ addrmap combpm {
external mem {
desc = "BPM filter table";
- memwidth = 8;
+ memwidth = 32;
mementries = 2**`C_W_ADDR_TABLE;
- } TABLE @0x200;
+ } FILTERTABLE;
};
--
GitLab