From 3df07a6ee3dd4f044be388e9907260fec2ed9c5f Mon Sep 17 00:00:00 2001
From: Romain Broucquart <romain.broucquart@synchrotron-soleil.fr>
Date: Mon, 7 Mar 2022 16:38:20 +0100
Subject: [PATCH] Add signals for debug on GTHE Common
* Add FB and REF lost signals
* Add output of GT ref clock (through buffers)
---
others/gthe_common.vhd | 38 ++++++++++++++++++++++++++++++--------
1 file changed, 30 insertions(+), 8 deletions(-)
diff --git a/others/gthe_common.vhd b/others/gthe_common.vhd
index fdbd8d3..dcae3ec 100644
--- a/others/gthe_common.vhd
+++ b/others/gthe_common.vhd
@@ -10,17 +10,27 @@ entity gthe_common is
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
+ -- Detection features
+ freerun_clk : in std_logic;
+
+ -- Buffered ref
+ buff_gtrefclk : out std_logic;
+
-- QPLL0 interface
qpll0reset : in std_logic;
qpll0lock : out std_logic;
qpll0outclk : out std_logic;
qpll0refclk : out std_logic;
+ qpll0fblost : out std_logic;
+ qpll0reflost : out std_logic;
-- QPLL0 interface
qpll1reset : in std_logic;
qpll1lock : out std_logic;
qpll1outclk : out std_logic;
- qpll1refclk : out std_logic
+ qpll1refclk : out std_logic;
+ qpll1fblost : out std_logic;
+ qpll1reflost : out std_logic
);
end entity gthe_common;
@@ -32,6 +42,8 @@ architecture struct of gthe_common is
ATTRIBUTE X_INTERFACE_INFO of gtrefclk_n: SIGNAL is "xilinx.com:interface:diff_clock:1.0 gtrefclk_diff CLK_N";
signal gtrefclk : std_logic;
+ signal gtrefclk_out2 : std_logic;
+
component combpm_gtwizard_gthe4_common_wrapper
port(
@@ -136,12 +148,22 @@ begin
)
port map (
O => gtrefclk,
- ODIV2 => open,
+ ODIV2 => gtrefclk_out2,
CEB => '0',
I => gtrefclk_p,
IB => gtrefclk_n
);
+ BUFG_GT_inst : BUFG_GT
+ port map (
+ O => buff_gtrefclk,
+ CE => '1',
+ CEMASK => '1',
+ CLR => '0',
+ CLRMASK => '1',
+ DIV => "000",
+ I => gtrefclk_out2
+ );
-- TRANSCEIVER COMMON BLOCK
gthe4_common_wrapper_inst: combpm_gtwizard_gthe4_common_wrapper
@@ -177,7 +199,7 @@ begin
GTHE4_COMMON_QPLL0CLKRSVD0 => "0",
GTHE4_COMMON_QPLL0CLKRSVD1 => "0",
GTHE4_COMMON_QPLL0FBDIV => "00000000",
- GTHE4_COMMON_QPLL0LOCKDETCLK => "0",
+ GTHE4_COMMON_QPLL0LOCKDETCLK(0) =>freerun_clk,
GTHE4_COMMON_QPLL0LOCKEN => "1",
GTHE4_COMMON_QPLL0PD => "0",
GTHE4_COMMON_QPLL0REFCLKSEL => "001",
@@ -185,7 +207,7 @@ begin
GTHE4_COMMON_QPLL1CLKRSVD0 => "0",
GTHE4_COMMON_QPLL1CLKRSVD1 => "0",
GTHE4_COMMON_QPLL1FBDIV => "00000000",
- GTHE4_COMMON_QPLL1LOCKDETCLK => "0",
+ GTHE4_COMMON_QPLL1LOCKDETCLK(0) =>freerun_clk,
GTHE4_COMMON_QPLL1LOCKEN => "1",
GTHE4_COMMON_QPLL1PD => "0",
GTHE4_COMMON_QPLL1REFCLKSEL => "001",
@@ -211,16 +233,16 @@ begin
GTHE4_COMMON_DRPRDY => open,
GTHE4_COMMON_PMARSVDOUT0 => open,
GTHE4_COMMON_PMARSVDOUT1 => open,
- GTHE4_COMMON_QPLL0FBCLKLOST => open,
+ GTHE4_COMMON_QPLL0FBCLKLOST(0) => qpll0fblost,
GTHE4_COMMON_QPLL0LOCK(0) => qpll0lock,
GTHE4_COMMON_QPLL0OUTCLK(0) => qpll0outclk,
GTHE4_COMMON_QPLL0OUTREFCLK(0) => qpll0refclk,
- GTHE4_COMMON_QPLL0REFCLKLOST => open,
- GTHE4_COMMON_QPLL1FBCLKLOST => open,
+ GTHE4_COMMON_QPLL0REFCLKLOST(0) => qpll0reflost,
+ GTHE4_COMMON_QPLL1FBCLKLOST(0) => qpll1reflost,
GTHE4_COMMON_QPLL1LOCK(0) => qpll1lock,
GTHE4_COMMON_QPLL1OUTCLK(0) => qpll1outclk,
GTHE4_COMMON_QPLL1OUTREFCLK(0) => qpll1refclk,
- GTHE4_COMMON_QPLL1REFCLKLOST => open,
+ GTHE4_COMMON_QPLL1REFCLKLOST(0) => qpll1fblost,
GTHE4_COMMON_QPLLDMONITOR0 => open,
GTHE4_COMMON_QPLLDMONITOR1 => open,
GTHE4_COMMON_REFCLKOUTMONITOR0 => open,
--
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