diff --git a/hdl/top_combpm_electron.vhd b/hdl/top_combpm_electron.vhd index 8b012fb58c3fe32f945469f43f2b0b7ce97be8f5..cc8f1ce320c0c27b413c5856af1596d52bcd95ed 100644 --- a/hdl/top_combpm_electron.vhd +++ b/hdl/top_combpm_electron.vhd @@ -9,6 +9,10 @@ use ieee.numeric_std.all; library xpm; use xpm.vcomponents.all; +library desyrdl; +use desyrdl.common.all; +use desyrdl.pkg_COMBPM.all; + entity top_combpm_electron is port( @@ -52,25 +56,8 @@ entity top_combpm_electron is m_axis_tready : in std_logic; -- AXI bus interface - s_axi_awaddr : in std_logic_vector(7 downto 0); - s_axi_awprot : in std_logic_vector(2 downto 0); - s_axi_awvalid : in std_logic; - s_axi_awready : out std_logic; - s_axi_wdata : in std_logic_vector(32-1 downto 0); - s_axi_wstrb : in std_logic_vector(32/8-1 downto 0); - s_axi_wvalid : in std_logic; - s_axi_wready : out std_logic; - s_axi_bresp : out std_logic_vector(1 downto 0); - s_axi_bvalid : out std_logic; - s_axi_bready : in std_logic; - s_axi_araddr : in std_logic_vector(7 downto 0); - s_axi_arprot : in std_logic_vector(2 downto 0); - s_axi_arvalid : in std_logic; - s_axi_arready : out std_logic; - s_axi_rdata : out std_logic_vector(32-1 downto 0); - s_axi_rresp : out std_logic_vector(1 downto 0); - s_axi_rvalid : out std_logic; - s_axi_rready : in std_logic + pi_s_top : in t_COMBPM_m2s; + po_s_top : out t_COMBPM_s2m ); end top_combpm_electron; @@ -165,7 +152,6 @@ architecture struct of top_combpm_electron is signal sync_reset : std_logic; signal usrclk : std_logic; signal rst : std_logic; - signal soft_reset : std_logic; signal frame_seq_cnt : std_logic_vector(15 downto 0); signal frame_valid_cnt : std_logic_vector(15 downto 0); @@ -178,18 +164,17 @@ architecture struct of top_combpm_electron is signal gt_datarx : std_logic_vector(15 downto 0); signal gt_powergood : std_logic; - signal gt_rxclkactive : std_logic; signal gt_rxcdrlock : std_logic; signal gt_rxresetdone : std_logic; signal gt_rxbyteisaligned : std_logic; signal gt_rxbyterealign : std_logic; signal gt_rxcommadet : std_logic; - signal gt_rxcommadeten : std_logic; - signal gt_rxresetdatapath : std_logic; - signal gt_rxresetplldatapath : std_logic; signal interface_ready : std_logic; + signal addrmap_w : t_addrmap_COMBPM_in; + signal addrmap_r : t_addrmap_COMBPM_out; + begin @@ -233,57 +218,32 @@ begin ---------------------- -- AXI-MM INTERFACE -- ---------------------- - axiitf_inst: entity work.combpm_ctrl_axi - generic map( - G_ADDR_W => 8 - ) - port map( - sfp_rxlos_i => sfp_rx_los, - sfp_modabs_i => sfp_mod_abs, - gt_powergood_i => gt_powergood, - gt_qplllock_i => qpll_lock, - gt_rxclkactive_i => gt_rxclkactive, - gt_rxcdrlock_i => gt_rxcdrlock, - gt_rxresetdone_i => gt_rxresetdone, - gt_rxbyteisaligned_i => gt_rxbyteisaligned, - gt_rxbyterealign_i => gt_rxbyterealign, - gt_rxcommadet_i => gt_rxcommadet, - gt_rxcommadeten_o => gt_rxcommadeten, - gt_rxrstdatapath_o => gt_rxresetdatapath, - gt_rxrstplldatapath_o => gt_rxresetplldatapath, - protocol_softreset_o => soft_reset, - - protocol_frameerror_i => frame_error, - protocol_seqframecnterror_i => cnt_seq_mismatch, - protocol_seqframediscont_i => seq_discontinuity, - framecnt_validframecnt_i => frame_valid_cnt, - framecnt_invalidframecnt_i => frame_invalid_cnt, - framerate_validframerate_i => frame_valid_rate, - framerate_invalidframerate_i => frame_invalid_rate, - frameseq_framecnt_i => frame_seq_cnt, - - clk => usrclk, - reset => sync_reset, - S_AXI_AWADDR => S_AXI_AWADDR, - S_AXI_AWPROT => S_AXI_AWPROT, - S_AXI_AWVALID => S_AXI_AWVALID, - S_AXI_AWREADY => S_AXI_AWREADY, - S_AXI_WDATA => S_AXI_WDATA, - S_AXI_WSTRB => S_AXI_WSTRB, - S_AXI_WVALID => S_AXI_WVALID, - S_AXI_WREADY => S_AXI_WREADY, - S_AXI_BRESP => S_AXI_BRESP, - S_AXI_BVALID => S_AXI_BVALID, - S_AXI_BREADY => S_AXI_BREADY, - S_AXI_ARADDR => S_AXI_ARADDR, - S_AXI_ARPROT => S_AXI_ARPROT, - S_AXI_ARVALID => S_AXI_ARVALID, - S_AXI_ARREADY => S_AXI_ARREADY, - S_AXI_RDATA => S_AXI_RDATA, - S_AXI_RRESP => S_AXI_RRESP, - S_AXI_RVALID => S_AXI_RVALID, - S_AXI_RREADY => S_AXI_RREADY - ); + blk_desyrdl: block + begin + inst_aximm: entity desyrdl.combpm + port map( + pi_clock => usrclk, + pi_reset => sync_resetn, + pi_s_top => pi_s_top, + po_s_top => po_s_top, + pi_addrmap => addrmap_w, + po_addrmap => addrmap_r + ); + + + --addrmap_w.ID.data.data <= C_ID; + --addrmap_w.VERSION.data.data <= C_VERSION; + addrmap_w.SFP.RXLOS.data(0) <= sfp_rx_los; + addrmap_w.SFP.MODABS.data(0) <= sfp_mod_abs; + addrmap_w.GT.POWERGOOD.data(0) <= gt_powergood; + addrmap_w.GT.QPLLLOCK.data(0) <= qpll_lock; + -- rxclkactive on test + addrmap_w.GT.RXCDRLOCK.data(0) <= gt_rxcdrlock; + addrmap_w.GT.RXRESETDONE.data(0) <= gt_rxresetdone; + addrmap_w.GT.RXBYTEISALIGNED.data(0) <= gt_rxbyteisaligned; + addrmap_w.GT.RXBYTEREALIGN.data(0) <= gt_rxbyterealign; + addrmap_w.GT.RXCOMMADET.data(0) <= gt_rxcommadet; + end block blk_desyrdl; -------------------------------------- -- LIBERA ELECTRON PROCOTOL DECODER -- @@ -307,7 +267,7 @@ begin m_axi_tready => m_axis_tready, mc_time => mc_time, - soft_reset => soft_reset, + soft_reset => addrmap_w.PROTOCOL.SOFTRESET.data(0), frame_seq_cnt => frame_seq_cnt, frame_valid_cnt => frame_valid_cnt, frame_invalid_cnt => frame_invalid_cnt, @@ -343,10 +303,10 @@ begin qpll1refclk_in(0) => qpll_ref_clk, -- Control - gtwiz_reset_rx_datapath_in(0) => gt_rxresetdatapath, - gtwiz_reset_rx_pll_and_datapath_in(0) => gt_rxresetplldatapath, + gtwiz_reset_rx_datapath_in => addrmap_r.GT.RXRSTDATAPATH.data, + gtwiz_reset_rx_pll_and_datapath_in => addrmap_r.GT.RXRSTPLLDATAPATH.data, rxbufreset_in => "0", - rxcommadeten_in(0) => gt_rxcommadeten, + rxcommadeten_in => addrmap_r.GT.RXCOMMADETEN.data, rx8b10ben_in => "1", rxmcommaalignen_in => "1", rxpcommaalignen_in => "1", @@ -356,7 +316,7 @@ begin -- Status gtwiz_userclk_tx_active_out => open, - gtwiz_userclk_rx_active_out(0) => gt_rxclkactive, + gtwiz_userclk_rx_active_out => addrmap_w.GT.RXCLKACTIVE.data, gtwiz_reset_tx_done_out => open, gtwiz_reset_rx_done_out(0) => gt_rxresetdone, gtpowergood_out(0) => gt_powergood,